Abstract: The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two ×16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these ×16 memories, the full address is provided. If the address is within the two columns of the second ×16 memory, the full address is also provided to the second ×16 memory. If the address is to the first of the ×16 memories, the second ×16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte.

Abstract: The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two ×16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these ×16 memories, the full address is provided. If the address is within the two columns of the second ×16 memory, the full address is also provided to the second ×16 memory. If the address is to the first of the ×16 memories, the second ×16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte.

Abstract: The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two ×16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these ×16 memories, the full address is provided. If the address is within the two columns of the second ×16 memory, the full address is also provided to the second ×16 memory. If the address is to the first of the ×16 memories, the second ×16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte.

Abstract: The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two x16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these x16 memories, the full address is provided. If the address is within the two columns of the second x16 memory; the full address is also provided to the second x16 memory. If the address is to the first of the x16 memories, the second x16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte.

Abstract: An integrated circuit architecture and test methods for use in designing, fabricating and testing mixed-signal application specific integrated circuits. The architecture comprises a plurality of mixed-signal integrated circuits, bidirectional buffers coupled to the integrated circuits that provide for circuit reconfigurability, a bidirectional digital/analog test bus, and a serial test controller coupled to the buffers that controls normal operation and testing of the integrated circuits. The controller and plurality of buffers cooperate to couple signals from signal pads to the integrated circuits to provide for "normal" operation thereof, and to re-route external test signals applied to selected signal pads to the integrated circuits to permit testing. Logic in the buffers provides for functional configurability, enabling them to be logically altered under control of the controller, and allowing the test bus to be connected directly to signal pads.

Abstract: A fast Fourier transform circuit formed on a single chip, including a fast multiplier-accumulator circuit which, in the preferred embodiment, employs a modified form of Booth's algorithm, an adder circuit, a read-only memory for storing FFT twiddle factors, and a random access memory for holding a set of input complex quantities and for receiving intermediate and final results in an in-place FFT operation. In the preferred embodiment, the FFT twiddle factors are stored in Booth's code for greater speed of operation. Control and timing circuitry on the same chip generates control signals and address codes in order to perform a sequence of butterfly computations by repeated use of the multiplier-accumulator and adder circuits, to generate FFT coefficients in the random access memory.

Abstract: There is described a logic element employing fixed threshold and variable threshold transistors electrically connected together to form a latch. The latch can be made to retain data by keeping certain internal nodes at a high or low voltage level. As such, it acts as an ordinary volatile semiconductor memory latch, whose data can be changed by externally overriding the internal voltage levels of the latch cell. Non-volatile storage capability is achieved by replacing one or several of the transistors in the latch by specially constructed transistors, whose threshold voltage can be raised or lowered upon application of a relatively high voltage pulse between their gate and substrate. By application of such a high voltage pulse, the data stored in the latch can be translated into controlled threshold shifts of the variable threshold transistors, which uniquely represent the initial latch state.

Abstract: A unique one chip counter arrangement and high-speed test circuit for an electronic timing device, such as a digital watch or clock. The counter arrangement is comprised of a plurality of separate divider stages interconnected with respect to one another in order to be rapidly tested in either a test mode or to be operated in a normal mode of operation by a minimum number of components which consume a relatively small amount of space.