Patents by Inventor Bruce Lee Morton
Bruce Lee Morton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9530463Abstract: A first input of a sense amplifier is connected to a first bitline, a second input of the sense amplifier is connected to a second bitline, a third input of the sense amplifier is coupled to a third bitline. The sense amplifier provides at an output an indicator of a storage state of a memory cell connected to the first bitline based upon information provided to the sense amplifier via the first, second, and third bitlines.Type: GrantFiled: July 31, 2015Date of Patent: December 27, 2016Assignee: TAGMATECH, LLCInventor: Bruce Lee Morton
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Patent number: 9099169Abstract: A first input of a sense amplifier is connected to a first bitline, a second input of the sense amplifier is connected to a second bitline, a third input of the sense amplifier is coupled to a third bitline. The sense amplifier provides at an output an indicator of a storage state of a memory cell connected to the first bitline based upon information provided to the sense amplifier via the first, second, and third bitlines.Type: GrantFiled: May 28, 2012Date of Patent: August 4, 2015Assignee: TAGMATECH, LLCInventor: Bruce Lee Morton
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Patent number: 8514631Abstract: Determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.Type: GrantFiled: June 7, 2011Date of Patent: August 20, 2013Assignee: Spansion LLCInventors: Bruce Lee Morton, Michael VanBuskirk
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Patent number: 8339873Abstract: A first input of a sense amplifier is connected to a first bitline, a second input of the sense amplifier is connected to a second bitline, a third input of the sense amplifier is coupled to a third bitline. The sense amplifier provides at an output an indicator of a storage state of a memory cell connected to the first bitline based upon information provided to the sense amplifier via the first, second, and third bitlines.Type: GrantFiled: April 27, 2010Date of Patent: December 25, 2012Inventor: Bruce Lee Morton
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Patent number: 8189410Abstract: A first input of a sense amplifier is connected to a first bitline, a second input of the sense amplifier is connected to a second bitline, a third input of the sense amplifier is coupled to a third bitline. The sense amplifier provides at an output an indicator of a storage state of a memory cell connected to the first bitline based upon information provided to the sense amplifier via the first, second, and third bitlines.Type: GrantFiled: April 27, 2010Date of Patent: May 29, 2012Inventor: Bruce Lee Morton
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Publication number: 20110235430Abstract: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.Type: ApplicationFiled: June 7, 2011Publication date: September 29, 2011Applicant: SPANSION LLC.Inventors: Bruce Lee Morton, Michael VanBuskirk
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Patent number: 7983089Abstract: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.Type: GrantFiled: June 6, 2008Date of Patent: July 19, 2011Assignee: Spansion LLCInventors: Bruce Lee Morton, Michael VanBuskirk
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Patent number: 7838342Abstract: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.Type: GrantFiled: June 6, 2008Date of Patent: November 23, 2010Assignee: Spansion LLCInventors: Bruce Lee Morton, Michael VanBuskirk
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Patent number: 7830716Abstract: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.Type: GrantFiled: June 6, 2008Date of Patent: November 9, 2010Assignee: Spansion LLCInventors: Bruce Lee Morton, Michael VanBuskirk
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Publication number: 20090303798Abstract: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.Type: ApplicationFiled: June 6, 2008Publication date: December 10, 2009Applicant: Spansion LLCInventors: Bruce Lee Morton, Michael VanBuskirk
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Publication number: 20090303795Abstract: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.Type: ApplicationFiled: June 6, 2008Publication date: December 10, 2009Applicant: Spansion LLCInventors: Bruce Lee Morton, Michael VanBuskirk
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Publication number: 20090303793Abstract: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.Type: ApplicationFiled: June 6, 2008Publication date: December 10, 2009Applicant: Spansion LLCInventors: Bruce Lee Morton, Michael VanBuskirk
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Patent number: 6128224Abstract: A method for writing data to non-volatile memory (50) involves alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). After writing, a verify erase (VE) operation and a verify program (VP) operation are performed to determine if multiple cycles are necessary. The method also permits refreshing data in the array without transferring the data onto a data bus for improved security. In one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete. The memory cell structure allows isolation of each bit in the array to avoid adverse effects on neighbor bits.Type: GrantFiled: April 9, 1999Date of Patent: October 3, 2000Assignee: Motorola, Inc.Inventors: Bruce Lee Morton, Michel Bron, Alexis Marquot, Graham Stout, Eric Boulian
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Patent number: 6075727Abstract: A method for writing to a bit of a non-volatile memory (50) by alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). Upon completion of the write operation a verify erase (VE) indication and a verify program (VP) indication are provided to a memory controller (58), which then determines if multiple cycles are necessary. The configuration of the memory cell allows isolation of each bit in the memory array to avoid effects of writes to neighbor bits. According to one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete.Type: GrantFiled: July 29, 1998Date of Patent: June 13, 2000Assignee: Motorola, IncInventors: Bruce Lee Morton, Michel Bron, Alexis Marquot, Graham Stout
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Patent number: 5754482Abstract: A memory (400) returns all bit lines to a predetermined voltage level optimum for subsequent fast sensing. The memory (400) includes precharge circuitry (106, 108, 110) which begins the precharge operation during the latching phase of a prior access. The precharge circuitry (106, 108, 110) precharges all bit lines, rather than a selected bit line, to the predetermined voltage level prior to address decoding. In order to prevent "walk-up", the memory (400) includes circuitry such as a switched capacitor (138, 140) which draws current from the bit lines to reduce the voltage on a bit line which drove a logic high level in an earlier cycle or which had an increased voltage due to capacitive cross-coupling to an adjacent bit line. The memory (400) may also include devices such as transmission gates (142, 144, 146) to couple together adjacent bit lines and thereby more evenly distribute the precharging.Type: GrantFiled: April 21, 1997Date of Patent: May 19, 1998Assignee: Motorola, Inc.Inventors: Jeffrey Yangming Su, Bruce Lee Morton, Chad Steven Gallun