Abstract: A method for transmitting data over a data bus with minimized digital control and data inter-symbol interference. The voltage level on the data bus is not permitted to reach the quiescent negated voltage level set by the bus terminator voltage. Additional time is provided for data detection circuitry to detect a first segment of data transferred over the data bus. A pause time is enabled after the data bus has been idle or paused for a prolonged period. After the first segment of data has been transferred, the method returns to normal operation by pausing for a normal period of time for data detection circuitry to detect subsequent segments of data transferred over the data bus. Additionally, during prolonged synchronous data transfers with unchanged data bits, the data bus is inverted and driven for further regulating the data bus voltage.

Abstract: A method and apparatus for correcting the timing skew of data signals in a parallel data transmission system, such as Small Computer System Interface (SCSI) data bus, relative to a receive clock in the data bus. The system separately corrects the receive clock duty cycle, and also features independent de-skewing of the rising and falling edges of a data waveform to improve timing accuracy of transmitted signals. The method and apparatus can be used without substantial changes to existing transmission system protocols, and can be implemented on an all-digital integrated circuit.

Abstract: A method for transmitting data via a data bus with minimized digital control and data inter-symbol interference. The voltage level on the bus is not permitted to reach the bus negated quiescent voltage level set by the bus terminator voltage. Additional time is provided for data detection circuitry to detect a first segment of data transferred over the bus. A pause time is enabled after the bus has been at idle/paused for a prolonged period. After the first segment of data has been transferred, the method returns to normal operation by pausing for a normal period of time for data detection circuitry to detect subsequent segments of data transferred over the bus. Additionally, during prolonged synchronous data transfers with unchanged data bits, the data bus is inverted and driven for further regulating the data bus voltage.

Abstract: A method for transmitting data over a data bus with minimized digital control and data inter-symbol interference. The voltage level on the data bus is not permitted to reach the quiescent negated voltage level set by the bus terminator voltage. Additional time is provided for data detection circuitry to detect a first segment of data transferred over the data bus. A pause time is enabled after the data bus has been idle or paused for a prolonged period. After the first segment of data has been transferred, the method returns to normal operation by pausing for a normal period of time for data detection circuitry to detect subsequent segments of data transferred over the data bus. Additionally, during prolonged synchronous data transfers with unchanged data bits, the data bus is inverted and driven for further regulating the data bus voltage.

Abstract: An embodiment of the invention provides a method for performing timing de-skew in order to properly receive digital computer information. A sequence of N clock pulses are generated at intervals having phases offset from one another by T/N, where N is at least 2, T is a duration of one bit-cell time, and one cycle of each of the clock phases has a duration of 2T. A test signal is generated at a transmitting portion. The test signal is received, and one of the generated sequences of clock pulses which is aligned with the test signal is identified. The identified one of the generated sequences of clock pulses is used to determine which one of the generated sequences of clock pulses and which polarity to use to receive data.

Abstract: A method for transmitting data via a data bus with minimized digital control and data inter-symbol interference. The voltage level on the bus is not permitted to reach the bus negated quiescent voltage level set by the bus terminator voltage. Additional time is provided for data detection circuitry to detect a first segment of data transferred over the bus. A pause time is enabled after the bus has been at idle/paused for a prolonged period. After the first segment of data has been transferred, the method returns to normal operation by pausing for a normal period of time for data detection circuitry to detect subsequent segments of data transferred over the bus. Additionally, during prolonged synchronous data transfers with unchanged data bits, the data bus is inverted and driven for further regulating the data bus voltage.

Abstract: Method and apparatus for optimizing data transfer over a terminated low voltage differential bus includes controlling parameters of a bus driver, a bus bias cancellation circuit, and other bus operating parameters, in response to received test results derived from test patterns sent over the bus at various transfer rates and parameter settings until optimized parameter settings within an acceptable error margin and at a highest available transfer rate are determined between a particular sending unit and a particular receiving unit on the bus.

Abstract: A circuit for monitoring and detecting data transfer protocol errors that occur during asynchronous transfer of data over a data bus. The circuit monitors bus request/acknowledge control lines in accordance with a predetermined handshaking protocol. In the event that an undefined or illegal logic state is detected on the data bus request or acknowledge control lines, the circuit provides an error value to the data sending entity. As a result of receiving this error value, the data sending entity can retry the data transmission over data bus.

Abstract: A method of providing error detection information for data transferred between a sender and a receiver interconnected via a bus in a data communication system. The sender transmits data to the receiver on the bus, generates error detection information for the transmitted data, transmits a notification signal to the receiver to indicate start of error detection information transfer, and transmits the error detection information to the receiver on the bus. The receiver generates error detection information for data received from the sender, and compares the receiver generated error detection information to error detection information received from the sender, posting an error condition in case of one or more mismatches.

Abstract: A circuit for counting events occurring between two different clock domains includes a gray code counter having at least two stages. The gray code counter is incremented by the event to be counted. Dual rank synchronizer circuit and delay flip/flops are coupled to the counter. The circuit includes a comparison logic circuit fed by outputs from the dual rank synchronizers and the delay flip/flops to produce an output signal having a binary value corresponding to a number of events that occurred between transitions of the second clock.

Abstract: A technique for verifying a pre-recorded header in a disk drive uses verification history to protect against errors that can cause verification failure. A head number, sector address, and upper track address (track MSB) are read from the disk and compared with corresponding expected values. The results of the 5 most recent comparisons are saved in three 5-bit memories. During each verification, a programmable selection and comparison circuit selects M of the stored indicators and determines whether at least N of them indicate a match. If so, the corresponding field is declared to be correctly verified, so that subsequent reads or writes to data blocks within the corresponding sector are allowed to proceed.

Abstract: An encoder in a data processing system generates, from a single m-bit coset leader constant, or symbol, a coset leader, which is a series of k m-bit symbols that resembles a random sequence of km bits. The encoder encodes the m-bit initial coset leader constant in a linear feedback shift register that is characterized by a maximum length polynomial over GF(2). The constants are produced by the register at the same times as the error correction symbols are produced by the encoder. The corresponding constants and symbols are then XOR'd together before the symbols are concatenated with the data symbols to form a code word for recording. A decoder similarly generates the coset leader from the initial constant. The decoder XOR's these constants with the error correction symbols in a retrieved code word as part of a demodulation operation.

Abstract: A method and system for verifying the integrity of data written to a mass memory medium. A local memory is directed by local memory control logic to store a data block that is received from a host microprocessor and that is to be written to the mass memory medium. The data block comprises a sequence of data symbols. An ECC encoder encodes the stored data block with error correction data. The error correction data comprises a sequence of error correction symbols that are appended to the data symbols. The data and error correction symbols are stored in the mass memory and immediately retrieved. An ECC decoder receives the retrieved data and error correction symbols from the mass memory and the data and error correction symbols of the encoded data block from the encoder. In response, the decoder generates an error status signal when more than a predetermined threshold number of the retrieved data and error correction symbols are improperly stored in the mass memory.

Abstract: A method and apparatus for identifying and synchronizing to two different fields in a disk drive employs different synchronization or "sync" patterns to reduce the chances of mis-identifying and false-identifying a field. Two very distinct synchronization patterns have been found that satisfy the d=1, k=7 run-length constraints of a data code used in the disk drive. During operation, one sync pattern is searched for to identify and synchronize to its associated field, then the field itself is read. This procedure is then repeated for the other sync pattern and its associated field. Also, the phase of a preamble preceding each sync character is established, so that the number of comparisons needed to find either sync character is reduced. A sync detector operates on cell pairs, and has a selector that selects which sync pattern to search for. The sync detector also has special features that enable it to find preamble and DC Erase fields in the disk cell stream.

Abstract: An error correction system generates a residue for data symbols encoded in accordance with an (n,k) code which has a distance "d" and a generator polynomial g(x). If the residue contains fewer than "T" non-zero symbols, where T<d/2, the data symbols are assumed to be error free. If there are T or more non-zero symbols, the data symbols are assumed to contain errors and the residue symbols are manipulated to correct the errors, if possible. The residue symbols are thus encoded using an encoder constructed in accordance with the generator polynomial g(x) by loading the residue symbols and shifting the encoder "m" times, where m is a factor of k. The number of non-zero symbols are then counted. If there are fewer than T non-zero symbols in the encoded residue, the encoded symbols are combined with the corresponding symbols in the code word. Thus the first encoded residue symbol is combined with the m.sup.th code word symbol, the second residue symbol is combined with the m+1.sup.

Abstract: A disk drive system provides all required synchronization, positioning, validation, and data functions within each disk sector. All of these functions are provided within two zones, a header section and a data section. The header section includes a preamble, a synchronization character and an address field, as well as servo information for track following. The data section of each sector includes a data preamble, a data synchronization character, a bad sector bit map, the data and data redundancy information. The header section of at least one sector in a track includes a short DC-erase field, a transitionless segment which is used in synchronization. To synchronize a read/write head to the disk, the system first detects the DC-erase field. The system next searches for the header premable and synchronization character. If it finds them within predetermined times, it then looks for a valid sector address to complete the synchronization.