Patents by Inventor Bruce M. Gilbert

Bruce M. Gilbert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6598120
    Abstract: Assigning a building block collector agent to receive acknowledgments from other building block agents is disclosed. A memory-line request is received from a requestor agent that is one of a number of agents. Each agent has a shared memory to share among the agents, as well as a cache to temporarily store a limited number of memory lines of the shared memories of the other agents. A collector agent, which is one of the agents, is dynamically assigned for receiving acknowledgments from the agents. This dynamic assignment is based on the type of memory line-related request, and/or the global state of the caches of the agents.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: July 22, 2003
    Assignee: International Business Machines Corporation
    Inventors: Thomas B. Berg, Bruce M. Gilbert
  • Publication number: 20030131154
    Abstract: Removing building blocks from partitions to which they have been bound is disclosed. A building block of a platform is removed from a partition of the platform by first halting activity by the partition on the building block. A first partition identifier of the building block indicates the partition of the building block. The building block joined the partition in a masterless manner. The resources of the building block are withdrawn from the partition, and the building block is deauthorized from the platform.
    Type: Application
    Filed: January 9, 2002
    Publication date: July 10, 2003
    Applicant: International Business Machines Corporation
    Inventors: Wayne A. Downer, Bruce M. Gilbert, Thomas D. Lovett, Mehul M. Shah
  • Publication number: 20030131200
    Abstract: A method and apparatus for providing cache coherence in a multiprocessor system which is configured into two or more nodes with memory local to each node and a tag and address crossbar system and a data crossbar system which interconnects all nodes. The disclosure is applicable to multiprocessor computer systems which utilize system memory distributed over more than one node and snooping of data states in each node which utilizes memory local to that node. Global snooping is used to provide a single point of serialization of data tags. A central crossbar controller examines cache state tags of a given address line for all nodes simultaneously and issues an appropriate reply back to a node requesting data while generating other data requests to any other node in the system for the purpose of maintaining cache coherence and supplying the requested data. The system utilizes memory local to each node by dividing such memory into local and remote categories which are mutually exclusive for any given cache line.
    Type: Application
    Filed: January 9, 2002
    Publication date: July 10, 2003
    Applicant: International Business Machines Corporation
    Inventors: Thomas B. Berg, Bruce M. Gilbert, Thomas D. Lovett
  • Publication number: 20030131067
    Abstract: A system and method of partitioning a multiprocessor or multinode computer system containing two or more partitions each of which contain at least three nodes or processors and a central hardware device communicating with a requestor node or processor, a target node or processor and at least one additional node or processor in the partition. The multiprocessor system architecture allows for partitioning resources to define separate subsystems capable of running different operating systems simultaneously. The method operates with the central device, a tag and address crossbar system, which transmits requests for data from the requestor node to the target node, but not to any of the additional nodes or processors which are not defined as part of a given partition. The method provides steps of assignment of definitions to physical ports with the central device corresponding with desired partitioning of resources within the system.
    Type: Application
    Filed: January 9, 2002
    Publication date: July 10, 2003
    Applicant: International Business Machines Corporation
    Inventors: Wayne A. Downer, Bruce M. Gilbert, Thomas D. Lovett
  • Publication number: 20030131214
    Abstract: A masterless approach binds multiprocessor building blocks to partitions of a computer system using identifiers and indicators. A number of building blocks communicate among each other to determine a partition to which each building block is to be partitioned. For each unique partition to which one or more of the building blocks is to be partitioned, the building blocks communicate among each other to determine building block uniqueness, and then each of the building blocks joins the partition. The building blocks share with one another their logical port identifiers, which uniquely identify the building block within a partition. A commit indicator of each building block indicates that the building block has committed itself to the partition and that its identifiers cannot be changed.
    Type: Application
    Filed: January 9, 2002
    Publication date: July 10, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wayne A. Downer, Bruce M. Gilbert, Thomas D. Lovett
  • Publication number: 20030131330
    Abstract: A masterless approach for binding building blocks to partitions is disclosed. Other blocks are first sent a first physical port identifier indicating a block's physical location, and a first partition identifier indicating the block's partition. Second physical port identifiers and second partition identifiers are received from the other blocks. The first physical port identifier and the second physical port identifiers of a subset of the other blocks are then sent to the subset, the second partition identifiers of the subset being equal to the first partition identifier. The first physical port identifier and the second physical port identifiers of the subset are also received from each block of the subset. A first logical port identifier indicating the block's logical location is sent to the subset, and second logical port identifiers are received from the subset. The block joins the partition indicated by the first partition identifier.
    Type: Application
    Filed: January 9, 2002
    Publication date: July 10, 2003
    Applicant: International Business Machines Corporation
    Inventors: Wayne A. Downer, Bruce M. Gilbert, Thomas D. Lovett, Mehul M. Shah
  • Publication number: 20030131043
    Abstract: A method of allocating hardware resources in a multiprocessor computer system which utilizes non-uniform memory access and distributed system resources across multiple nodes. The disclosure provides a method for allocating system resources across multiple nodes of a system communicating through a hardware device comprised of a tag and address crossbar system interconnecting node control devices. The method provides for allocation of transaction units or transaction identifiers in an allocating component for use in a multiple target component which may be in a distinct target node within the multiple node system.
    Type: Application
    Filed: January 9, 2002
    Publication date: July 10, 2003
    Applicant: International Business Machines Corporation
    Inventors: Thomas B. Berg, Bruce M. Gilbert, Stacey G. Lloyd
  • Patent number: 6591370
    Abstract: A multinode multiprocessor computer system with distributed local clocks wherein a local clock may be synchronized with other clocks in the system without affecting the operation of the other clocks. A local clock to be synchronized is reset and counts an elapsed time since the reset. Simultaneously with resetting the local clock, a clock value from a clock on a source node is stored. The clock value from the source node is copied to the node to be synchronized and added to the elapsed time. The resulting summation is then stored in the local clock to be synchronized. As a result, the local clock is synchronized to the clock on the source node. In one system embodiment, the local clock includes a dynamic register and a base register and an adder adds the two portions together to generate an output of the local clock. For a node being synchronized, the dynamic portion is reset and allowed to count the elapsed time while the base portion is loaded with a clock value copied from the source node.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: July 8, 2003
    Assignee: International Business Machines Corporation
    Inventors: Thomas D. Lovett, Bruce M. Gilbert, Thomas B. Berg
  • Patent number: 6295584
    Abstract: An apparatus and method is disclosed for allowing a multiprocessor computer system with shared memory distributed among multiple nodes to appear like a single-node environment. The single-node environment is implemented with a memory map that has a unique address for every memory location in the system. Overlapping address spaces in the multinode environment are also assigned unique representative addresses that are translated to actual addresses in conformance with the multinode environment. The apparatus and method allows a wide variety of operating systems to be run on the multinode environment. Additionally, industry standard BIOS and chip sets can be used.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: September 25, 2001
    Assignee: International Business Machines Corporation
    Inventors: Donald R. DeSota, Bruce M. Gilbert, Thomas D. Lovett, Robert J. Safranek, Kenneth Frank Dove
  • Patent number: 5900020
    Abstract: A method and apparatus for maintaining processor consistency in a multiprocessor computer such as a multinode computer system are disclosed. A processor proceeds with write operations before its previous write operations complete, while processor consistency is maintained. A write operation begins with a request by the processor to invalidate copies of the data stored in other nodes. This current invalidate request is queued while acknowledging to the processor that the request is complete even though it has not actually completed. The processor proceeds to complete the write operation by changing the data. It can then execute subsequent operations, including other write operations. The queued request, however, is not transmitted to other nodes in the computer until all previous invalidate requests by the processor are complete. This ensures that the current invalidate request will not pass a previous invalidate request.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: May 4, 1999
    Assignee: Sequent Computer Systems, Inc.
    Inventors: Robert J. Safranek, Thomas D. Lovett, Robert T. Joersz, Bruce M. Gilbert