Abstract: A method of generating simulated data signals, data processing system and software model are disclosed. The method comprises the steps of: a) providing input data signals to a component of a data processing apparatus; b) capturing a representation of the input data signals; c) providing a software model operable to simulate the behaviour of the component of the data processing apparatus; and d) executing the software model using the captured representation of the input data signals to generate simulated data signals representing the behaviour of the component of the data processing apparatus in response to the input data signals. Using a software model to emulate the behaviour of the component in response to the input data signals obviates the need to manufacture a test chip for debugging purposes. Also, any timing issues which arise when using a test chip can be obviated by using a software model.

Abstract: Interconnect logic is provided for coupling master logic units and slave logic units within a data processing apparatus to enable transactions to be performed. Each transaction comprises an address transfer from a master logic unit to a slave logic unit and one or more data transfers between that master logic unit and that slave logic unit. The interconnect logic comprises a plurality of connection paths for providing at least one address channel for carrying address transfers and at least one data channel for carrying data transfers, and control logic is used to control the use of the at least one address channel and the at least one data channel in order to enable the transactions to be performed.

Abstract: A data processing apparatus and method of arbitration within such a data processing apparatus are provided for arbitrating between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit of that data processing apparatus. The plurality of paths include a shared connection, the data processing apparatus having a plurality of initiator logic elements for initiating transfers and a plurality of recipient logic elements for receiving transfers, for each transfer the corresponding path coupling the initiator logic element responsible for initiating that transfer with the recipient logic element destined to receive that transfer. At least one of the recipient logic elements that is destined to receive one of the transfers has a storage element associated therewith which is operable to temporarily store transfer data of that transfer.

Abstract: Bus logic, a data processing apparatus and a method is disclosed. The bus logic is operable to couple a plurality of master logic units with a plurality of slave logic units to enable data transfers to occur, each master logic unit being operable to perform an address transfer which, when received by a specified one of the plurality of slave logic units, causes an associated data transfer to be performed between that master logic unit and the specified one of the plurality of slave logic units, each of the plurality of slave logic units being required to complete a data transfer, once initiated, prior to performing any further data transfers, at least one of the plurality of slave logic units being operable to perform data transfers in an order which differs from that in which associated address transfers were received by that slave logic unit.

Abstract: A data processing apparatus and method of arbitration within such a data processing apparatus are provided for arbitrating between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit of that data processing apparatus. The plurality of paths include a shared connection, the data processing apparatus having a plurality of initiator logic elements for initiating transfers and a plurality of recipient logic elements for receiving transfers, for each transfer the corresponding path coupling the initiator logic element responsible for initiating that transfer with the recipient logic element destined to receive that transfer. At least one of the recipient logic elements that is destined to receive one of the transfers has a storage element associated therewith which is operable to temporarily store transfer data of that transfer.

Abstract: A data processing system is provided with a bus having separate write channels W and read channels R via which bus transactions are made. Bus transaction buffers 34 are provided within the bus structure to buffer write requests, particularly so as to alleviate problems associated with relatively slow bus slaves. The bus transaction buffers 34 are responsive to the memory addresses associated with write requests and read requests which pass through them to identify those to the same memory address, or memory addresses within a predetermined range, so as to either ensure a strict correct ordering of those transactions, read to follow write, or to satisfy a read following a write with a buffered write data value and then flushing the read request such that it does not reach its final destination.

Abstract: An integrated circuit 2 is provided with multiple bus masters 4, 6 and multiple bus slaves 8, 10, 12, communicating via a multi-channel communication bus. A separate write data channel, read data channel and write response channel are provided as well as a separate write address channel and a read address channel. The provision of a dedicated write response channel frees the read data channel to be more efficiently used for the transfer of read data. Transactions may be burst mode transactions with a single write response corresponding to the write transaction as a whole.

Abstract: A bus master 2, 4 sends write transactions to a bus slave 8 which include separate write addresses AW and write data WD. Write transaction identifiers AWID, WID are associated with these write addresses and write data. The bus slave can accept multiple write addresses such that there can be copending write transactions to the same bus slave. The bus slave uses the write transaction identifiers to correlate interleaved write data for the co-pending write transactions with their write addresses.

Abstract: A data processing apparatus and method of handling write transactions in such an apparatus is provided. The apparatus has a plurality of devices, and bus circuitry providing connection paths between the plurality of devices. At least one of the devices has a bus master interface operable to generate write transactions for output via the bus circuitry, whilst at least one of the devices has a bus slave interface operable to receive the write transactions from the bus circuitry. A write transaction includes transferring a write address from a bus master interface to a bus slave interface and separately transferring write data from the bus master interface to the bus slave interface. In accordance with embodiments of the present invention, the bus master interface is allowed to generate a write transaction such that the write data is received at the bus slave interface before the associated write address. This leads to a significant decrease in the complexity of the apparatus.

Abstract: The present invention provides a data processing apparatus and method for handling a multi-access instruction of the type which specifies that an access request of a first type and an access request of a second type should be performed without any intervening accesses taking place. The data processing apparatus has a processor operable to execute instructions, and a first master logic unit and a second master logic unit operable to process access requests generated during execution of those instructions. The access requests specify accesses to a slave device, with the first master logic unit being operable to access the slave device via a first bus, and the second master logic unit being operable to access the slave device via a second bus.

Abstract: A data processing apparatus comprises at least one source processor core (110), at least one destination processor core (120), a message handler (130) and a bus arrangement (150) providing a data communication path between the source core, the destination core and the message handler. The message handler (130) has plurality of message-handling modules (132-1 to 132-3). At least one of the message-handling modules (132-1 to 132-3) is programmable to enable exclusive control by a specified source processor core.

Abstract: A direct memory access controller for controlling data transfer between a data source and a data destination comprising: a read/write port operable to receive data from said data source via a source bus and to output said received data to said data destination via a destination bus; wherein said direct memory access controller is operable in response to a predetermined number of clock pulses, to control said read/write port to output said received data said predetermined number of clock pulses after having received it. Also a direct memory access controller for controlling data transfer between a data source and a data destination comprising: a single read/write port comprising a read channel operable to receive data from said data source via a read path on a bus and a write channel operable to output said received data to said data destination via a write path on said bus, said read and write channel being operable to perform data reads and writes independently of each other.

Abstract: A data processing apparatus comprises at least one source processor core (110), at least two destination processor cores (120), a message handler (130) and a bus arrangement (150) providing a data communication path between the source core, the destination cores and the message handler. The message handler (130) has plurality of message-handling modules (132-1 to 132-3). At least one of the message-handling modules has a message receipt indicator that is modifiable by each of the destination processor cores to indicate that a message has been received at its destination. This message-handling module also has a transmission completion detector operable to detect, in dependence upon a message receipt indicator value that a message has been received by all of the at least two destination processor cores and to initiate transmission of an acknowledgement signal to the source processor core.

Abstract: The present invention provides a data processing apparatus and method for handling a multi-access instruction of the type which specifies that an access request of a first type and an access request of a second type should be performed without any intervening accesses taking place. The data processing apparatus has a processor operable to execute instructions, and a first master logic unit and a second master logic unit operable to process access requests generated during execution of those instructions. The access requests specify accesses to a slave device, with the first master logic unit being operable to access the slave device via a first bus, and the second master logic unit being operable to access the slave device via a second bus.

Abstract: A system for the debugging of integrated circuit designs containing a plurality of macrocells A, B and C utilises multiplexers 68, 70 and 72 associated with external output connections to select either a normal external output signal or a diagnostic internal signal. In operation, a primary integrated circuit and a tracking integrated circuit are supplied with identical input signals and so adopt identical states. The primary integrated circuit selects the normal external output signals whilst the tracking integrated circuit selects for diagnostic purposes predetermined internal signals. A further tracking integrated circuit 74 may be provided that corresponds to one of the macrocells A within the primary integrated circuit and the tracking integrated circuit to provide further details of the operation of this macrocell.