Abstract: Semiconductor manufacturing processes include forming conventional channel field effect transistors (FETs) and deeply depleted channel (DDC) FETs on the same substrate and selectively forming a plurality of gate stack types where those different gate stack types are assigned to and formed in connection with one or more of a conventional channel NFET, a conventional channel PFET, a DDC-NFET, and a DDC-PFET in accordance a with a predetermined pattern.

Abstract: Semiconductor manufacturing processes include forming conventional channel field effect transistors (FETs) and deeply depleted channel (DDC) FETs on the same substrate and selectively forming a plurality of gate stack types where those different gate stack types are assigned to and formed in connection with one or more of a conventional channel NFET, a conventional channel PFET, a DDC-NFET, and a DDC-PFET in accordance a with a predetermined pattern.

Abstract: Semiconductor manufacturing processes include forming conventional channel field effect transistors (FETs) and deeply depleted channel (DDC) FETs on the same substrate and selectively forming a plurality of gate stack types where those different gate stack types are assigned to and formed in connection with one or more of a conventional channel NFET, a conventional channel PFET, a DDC-NFET, and a DDC-PFET in accordance a with a predetermined pattern.

Abstract: Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.

Abstract: Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.

Abstract: A camera system may include an optics stack including two substrates secured together in a vertical direction and an optical system on the two substrates, the two substrates having exposed sides, a detector on a detector substrate, and a stray light blocker directly on at least some sides of the optics stack.

Abstract: A method of making a plurality of sealed assemblies is provided which includes a) assembling a first element to a second element so that a bottom surface of the first element faces downwardly toward a front surface of the second element and a top surface of the first element faces upwardly away from the second element; and (b) forming ring seals surrounding regions of the front surface of the second element by introducing flowable material between the first element and the second element from the top surface of the first element through openings in the first element. A chip is provided which includes: (a) a body defining a front surface and one or more circuit elements on or within the body; (b) one or more bond pads exposed at the front surface in a bond pad region; and (c) a metallic ring exposed at the front surface, the ring substantially surrounding the bond pad region. Sealed chip assemblies are formed by sealing an array of the chips, e.g., in wafer form, to a cap element.

Abstract: A capped chip is provided which includes a chip having a front surface, a plurality of conductive features exposed at the front surface and a cap. The cap has an inner surface facing the front surface of the chip, an outer surface opposite the inner surface, and a through hole extending from the outer surface to the inner surface. A conductive interconnect extends at least partially through the through hole. The interconnect includes a conductive article which occupies a substantial portion of a volume of the interconnect and the interconnect further includes a flowable conductive medium which joins the conductive article to at least one of the plurality of conductive features of the chip or to the cap.

Abstract: Capped chips and methods of forming a capped chip are provided in which electrical interconnects are made by conductive elements which extend from bond pads of a chip at least partially through a plurality of through holes of a cap. The electrical interconnects may be solid, so as to form seals extending across the through holes. In some cases, stud bumps extend from the bond pads, forming parts of the electrical interconnects. In some cases, a fusible conductive medium forms a part of the electrical interconnects.

Abstract: Image sensors are provided having a plurality of photodetectors in a detector layer Optionally, an optically transparent substrate is provided for a rear-illuminated sensor architecture. The photodetectors may be arranged in three or more arrays. Typically, each array is contiguous and is associated with light of a different color and/or wavelength. In addition, the arrays may be coplanar, or, in the alternative, located at increasing distances from a light-receiving surface in an at least partially nonoverlapping manner. Also provided are image sensor packages.

Abstract: A microelectronic package may include front and rear covers overlying the front and rear surfaces of a microelectronic element such as an infrared sensor and spaces between the microelectronic element and the covers to provide thermal isolation. A sensing unit including a microelectronic package may include a reflector spaced from the front cover to provide an analyte space, and the microelectronic element may include an emitter and a detector so that radiation directed from the emitter will be reflected by the sensor to the detector, and such radiation will be affected by the properties of the analyte in the analyte space. Such a unit provides a compact, economical chemical sensor. Other packages include elements such as valves for passing fluids into and out of the spaces within the package itself.

Abstract: A connection component including a flexible substrate having a top surface and a bottom surface, a layer of a compliant, dielectric material overlying the top surface of the substrate, the compliant material layer having a top surface remote from the substrate, an array of flexible, conductive leads having first ends attached to terminals accessible at the bottom surface of the substrate and second ends adjacent the top surface of the compliant layer, wherein each lead comprises a core of a first conductive material surrounded by a layer of a second conductive material, the second conductive material having a greater yield strength than the first conductive material.

Abstract: Capped chips and methods of forming a capped chip are provided in which electrical interconnects are made by conductive elements which extend from bond pads of a chip at least partially through a plurality of through holes of a cap. The electrical interconnects may be solid, so as to form seals extending across the through holes. In some cases, stud bumps extend from the bond pads, forming parts of the electrical interconnects. In some cases, a fusible conductive medium forms a part of the electrical interconnects.

Abstract: A method of making a chip assembly is provided which includes the steps of: (a) assembling (i) a capped chip including a chip, a cap overlying a front surface of the chip and a sacrificial layer overlying the cap with (ii) one or more further components; and (b) after the assembling step, removing the sacrificial layer from the capped chip. A method of making a plurality of capped chip assemblies is provided which includes the steps of: (a) assembling a lid member and a chip member including a plurality of chips to one another so that the lid member overlies the chip member and a top surface of the lid member faces away from the chip member; (b) severing the lid member and chip member to form a plurality of individual units each including one or more of the chips and a portion of the lid member; (c) providing a sacrificial layer overlying the top surface of the lid member prior to the severing step; and (d) removing the sacrificial layer after the severing step.

Abstract: A method of making a plurality of sealed assemblies is provided which includes a) assembling a first element to a second element so that a bottom surface of the first element faces downwardly toward a front surface of the second element and a top surface of the first element faces upwardly away from the second element; and (b) forming ring seals surrounding regions of the front surface of the second element by introducing flowable material between the first element and the second element from the top surface of the first element through openings in the first element. A chip is provided which includes: (a) a body defining a front surface and one or more circuit elements on or within the body; (b) one or more bond pads exposed at the front surface in a bond pad region; and (c) a metallic ring exposed at the front surface, the ring substantially surrounding the bond pad region. Sealed chip assemblies are formed by sealing an array of the chips, e.g., in wafer form, to a cap element.

Abstract: A procedure for temporally isolating an environmentally dependent integrated circuit fault includes the steps of determining a marginally failing and a minimally passing environmental condition corresponding to the fault; identifying a clock cycle Tmax at which the fault was first detected; determining a candidate clock cycle at which the fault may have occurred; and iteratively a) applying test pattern subsets from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition; b) applying remaining test patterns under the minimally passing environmental condition; and c) adjusting the candidate clock cycle based upon whether the fault occurred during test pattern subset application up through the candidate clock cycle under the marginally failing environmental condition. Candidate clock cycle adjustment in accordance with a binary search technique enables determination of an exact clock cycle at which the fault occurred in a maximum of Log2 (Tmax+1) iterations.

Abstract: A procedure for temporally isolating an environmentally dependent integrated circuit fault includes the steps of determining a marginally failing and a minimally passing environmental condition corresponding to the fault; identifying a clock cycle Tmax at which the fault was first detected; determining a candidate clock cycle at which the fault may have occurred; and iteratively a) applying test pattern subsets from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition; b) applying remaining test patterns under the minimally passing environmental condition; and c) adjusting the candidate clock cycle based upon whether the fault occurred during test pattern subset application up through the candidate clock cycle under the marginally failing environmental condition.

Abstract: A connection component including a flexible substrate having a top surface and a bottom surface, a layer of a compliant, dielectric material overlying the top surface of the substrate, the compliant material layer having a top surface remote from the substrate, an array of flexible, conductive leads having first ends attached to terminals accessible at the second surface of the substrate and second ends adjacent the top surface of the compliant layer, wherein each the lead comprises a core of a first conductive material surrounded by a layer of a second conductive material, the second conductive material having a greater yield strength than the first conductive material.

Abstract: A method of making a microelectronic package having an array of resilient leads includes providing a first element having a plurality of conductive leads at a first surface thereof, the conductive leads having terminal ends permanently attached to the first element and tip ends remote from the terminal ends, the tip ends being movable relative to the terminal ends. A second element having a plurality of contacts on a first surface thereof is then juxtaposed with the first surface of the first element, and the tip ends of the conductive leads are connected with the contacts of the second microelectronic element. The first and second elements are then moved away from one another so as to vertically extend the conductive leads between the first and second elements. After the moving step, a layer of a spring-like conductive material is formed over the conductive leads to form composite leads.

Abstract: A method of making a microelectronic package having an array of resilient leads includes providing a first element having a plurality of conductive leads at a first surface thereof, the conductive leads having terminal ends permanently attached to the first element and tip ends remote from the terminal ends, the tip ends being movable relative to the terminal ends. A second element having a plurality of contacts on a first surface thereof is then juxtaposed with the first surface of the first element, and the tip ends of the conductive leads are connected with the contacts of the second microelectronic element. The first and second elements are then moved away from one another so as to vertically extend the conductive leads between the first and second elements. After the moving step, a layer of a spring-like conductive material is formed over the conductive leads to form composite leads.