Patents by Inventor Bruce Miao

Bruce Miao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS OF STRATIFYING AND TREATING CORONAVIRUS INFECTION
    Publication number: 20240132976
    Abstract: The subject matter disclosed herein is generally directed to stratifying and treating coronavirus infections based on intrinsic immune states.
    Type: Application
    Filed: February 18, 2022
    Publication date: April 25, 2024
    Inventors: Alexander K. Shalek, Jose Ordovas-Montanes, Carly Ziegler, Sarah Glover, Bruce Horwitz, Vincent Miao, Anna Owings, Andrew Navia, Ying Tang, Joshua Bromley
  • Shallow trench isolation recess process flow for vertical field effect transistor fabrication
    Patent number: 10388651
    Abstract: A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with a pitch P. The first and second regions are separated by an isolation region with spacing S, wherein S is greater than P. A first insulating layer is deposited and recessed to a target depth in the first region, and to a second depth in the isolation region. The second depth is lower than the target depth. A first etch stop layer is formed over the recessed first insulating layer, and a second insulating layer is formed over the first etch stop layer to increase a level of insulating material in the isolation region to the same target depth in the first device region. The recessed first insulating layer, first etch stop layer, and second insulating layer form a uniform thickness shallow trench isolation layer.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Bruce Miao, Xin Miao
  • Shallow trench isolation recess process flow for vertical field effect transistor fabrication
    Patent number: 9985021
    Abstract: A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with a pitch P. The first and second regions are separated by an isolation region with spacing S, wherein S is greater than P. A first insulating layer is deposited and recessed to a target depth in the first region, and to a second depth in the isolation region. The second depth is lower than the target depth. A first etch stop layer is formed over the recessed first insulating layer, and a second insulating layer is formed over the first etch stop layer to increase a level of insulating material in the isolation region to the same target depth in the first device region. The recessed first insulating layer, first etch stop layer, and second insulating layer form a uniform thickness shallow trench isolation layer.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Bruce Miao, Xin Miao
  • SHALLOW TRENCH ISOLATION RECESS PROCESS FLOW FOR VERTICAL FIELD EFFECT TRANSISTOR FABRICATION
    Publication number: 20180096992
    Abstract: A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with a pitch P. The first and second regions are separated by an isolation region with spacing S, wherein S is greater than P. A first insulating layer is deposited and recessed to a target depth in the first region, and to a second depth in the isolation region. The second depth is lower than the target depth. A first etch stop layer is formed over the recessed first insulating layer, and a second insulating layer is formed over the first etch stop layer to increase a level of insulating material in the isolation region to the same target depth in the first device region. The recessed first insulating layer, first etch stop layer, and second insulating layer form a uniform thickness shallow trench isolation layer.
    Type: Application
    Filed: October 30, 2017
    Publication date: April 5, 2018
    Inventors: Zhenxing Bi, Kangguo Cheng, Bruce Miao, Xin Miao
  • SHALLOW TRENCH ISOLATION RECESS PROCESS FLOW FOR VERTICAL FIELD EFFECT TRANSISTOR FABRICATION
    Publication number: 20180096989
    Abstract: A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with a pitch P. The first and second regions are separated by an isolation region with spacing S, wherein S is greater than P. A first insulating layer is deposited and recessed to a target depth in the first region, and to a second depth in the isolation region. The second depth is lower than the target depth. A first etch stop layer is formed over the recessed first insulating layer, and a second insulating layer is formed over the first etch stop layer to increase a level of insulating material in the isolation region to the same target depth in the first device region. The recessed first insulating layer, first etch stop layer, and second insulating layer form a uniform thickness shallow trench isolation layer.
    Type: Application
    Filed: April 26, 2017
    Publication date: April 5, 2018
    Inventors: Zhenxing Bi, Kangguo Cheng, Bruce Miao, Xin Miao
  • Shallow trench isolation recess process flow for vertical field effect transistor fabrication
    Patent number: 9824934
    Abstract: A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with a pitch P. The first and second regions are separated by an isolation region with spacing S, wherein S is greater than P. A first insulating layer is deposited and recessed to a target depth in the first region, and to a second depth in the isolation region. The second depth is lower than the target depth. A first etch stop layer is formed over the recessed first insulating layer, and a second insulating layer is formed over the first etch stop layer to increase a level of insulating material in the isolation region to the same target depth in the first device region. The recessed first insulating layer, first etch stop layer, and second insulating layer form a uniform thickness shallow trench isolation layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Bruce Miao, Xin Miao