Patents by Inventor Bruce Odekirk

Bruce Odekirk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8436367
    Abstract: A SiC Power Semiconductor device of the Field Effect Type (MOSFET, IGBT or the like) with “muted” channel conduction, negative temperature coefficient of channel mobility, in situ “ballasted” source resistors and optimized thermal management of the cells for increased Safe Operating Area is described. Controlling the location of the Zero Temperature Crossover Point (ZTCP) in relationship to the drain current is achieved by the partition between the “active” and “inactive” channels and by adjusting the mobility of the carriers in the channel for the temperature range of interest. The “Thermal management” is realized by surrounding the “active” cells/fingers with “inactive” ones and the “negative” feedback of the drain/collector current due to local increase of the gate bias is achieved by implementing in-situ “ballast” resistors inside of each source contact.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: May 7, 2013
    Assignee: Microsemi Corporation
    Inventors: Dumitru Sdrulla, Bruce Odekirk, Marc Vandenberg
  • Publication number: 20110049532
    Abstract: A dual-mesa static induction transistor (SIT) structure includes a silicon carbide substrate having a layer arrangement formed thereon. Laterally spaced ion implanted gate regions are defined in the layer arrangement. Source regions are defined in the layer arrangement. Each of the source regions can include a channel mesa having a source mesa disposed thereon. The source mesa includes sidewalls relative to a principal plane of the substrate defining a horizontal dimension thereof. The channel mesa includes slanted sidewalls relative to the source mesa and the principal plane of the substrate. Also disclosed is a method of fabricating a dual-mesa SiC transistor device. The method includes implanting ions at a normal relative to a principal plane of the substrate to form gate junctions in upper portions of the substrate and lateral portions of the slanted channel mesas.
    Type: Application
    Filed: August 27, 2010
    Publication date: March 3, 2011
    Applicant: MICROSEMI CORPORATION
    Inventors: Bruce Odekirk, Francis K. Chai, Edward W. Maxwell
  • Publication number: 20110037139
    Abstract: A merged PN/Schottky diode is provided having a substrate of a first conductivity type and a grid of doped wells of the second conductivity type embedded in the substrate. A Schottky barrier metal layer makes a Schottky barrier contact with the surface of the substrate above the grid. Selected embedded wells in the grid may make electrical contact to the Schottky bather metal layer, while most embedded wells do not. The diode forward voltage drop is reduced for the same diode area with reverse blocking benefits similar to a conventional JBS structure.
    Type: Application
    Filed: October 26, 2010
    Publication date: February 17, 2011
    Applicant: MICROSEMI CORPORATION
    Inventors: Feng Zhao, Bruce Odekirk, Dumitru Sdrulla
  • Patent number: 7851881
    Abstract: A merged PN/Schottky diode is provided having a substrate of a first conductivity type and a grid of doped wells of the second conductivity type embedded in the substrate. A Schottky barrier metal layer makes a Schottky barrier contact with the surface of the substrate above the grid. Selected embedded wells in the grid make a Schottky barrier contact to the Schottky barrier metal layer, while most embedded wells do not. The diode forward voltage drop is reduced for the same diode area with reverse blocking benefits similar to a conventional JBS structure.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: December 14, 2010
    Assignee: Microsemi Corporation
    Inventors: Feng Zhao, Bruce Odekirk, Dumitru Sdrulla
  • Patent number: 6388272
    Abstract: Ohmic and rectifying contacts to a TaC layer on an n-type or p-type area of an SiC substrate are formed by depositing a WC layer over the TaC layer, followed by a metallic W layer. Such contacts are stable to at least 1150° C. Electrodes connect to the contacts either directly or via a protective bonding layer such as Pt or PtAu alloy through a dielectric layer.
    Type: Grant
    Filed: July 27, 2000
    Date of Patent: May 14, 2002
    Assignee: Caldus Semiconductor, Inc.
    Inventor: Bruce Odekirk
  • Publication number: 20020024050
    Abstract: Ohmic and rectifying contacts to a TaC layer on an n-type or p-type area of an SiC substrate are formed by depositing a WC layer over the TaC layer, followed by a metallic W layer. Such contacts are stable to at least 1150° C. Electrodes connect to the contacts either directly or via a protective bonding layer such as Pt or PtAu alloy through a dielectric layer.
    Type: Application
    Filed: July 25, 2001
    Publication date: February 28, 2002
    Applicant: Caldus Semiconductor, Inc.
    Inventor: Bruce Odekirk
  • Patent number: 5143857
    Abstract: A method of fabricating an integrated circuit comprises providing a heavily compensated substrate having a source region, a drain region and a third region, each of a first conductivity type, and introducing dopant of a second conductivity type into the substrate to surround the third region.
    Type: Grant
    Filed: July 30, 1990
    Date of Patent: September 1, 1992
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Eric P. Finchem, William A. Vetanen, Bruce Odekirk, Irene G. Beers