Abstract: A driver circuit includes two pull-up portions coupled respectively between VDD and first and second driver output nodes and two pull-down sections coupled respectively between ground and third and fourth driver output nodes. The driver circuit is configurable as an RS485 driver or a CAN driver. The active diodes in the pull-up sections are turned off when necessary to prevent unwanted reverse currents between the first and second output nodes and VDD. The active diodes in the pull-down sections are turned off when necessary to prevent unwanted reverse current between ground and the third and fourth output nodes.

Abstract: Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

Abstract: Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

Abstract: Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

Abstract: Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

Abstract: According to one embodiment, a power-efficient, low noise photoplethysmographic (PPG) sensor module is provided herein comprising at least one light emitting diode (LED) and at least one photodetector. The LED is generally configured for emitting light, and is positioned on the PPG sensor module for transmitting the emitted light into biological tissue. The photodetector is generally configured for detecting a portion of the light that is transmitted by the LED into the biological tissue and reflected back to the photodetector. The photodetector is an elongated photodetector having a longer dimension that is at least 1.5 times larger than a shorter dimension of the elongated photodetector. By positioning the elongated photodetector on the PPG sensor module, such that the longer dimension is facing towards the first LED, the elongated photodetector is configured to collect substantially more of the reflected light, thereby increasing the signal-to-noise ratio of the detected signal.

Abstract: Stacked layers of non-continuous opaque layer structures are disclosed herein that may be configured to block radiation such as visible light or other forms of light, while at the same time allowing penetration of ambient gases. In one example, such non-continuous opaque layer structures may be configured as stacked non-continuous metal layer structures that together fully block penetration of radiation while at the same provide sufficient open spaces between and/or within the metal layer segments of a given integrated circuit layer to meet maximum metal spacing rules. In another example, such non-continuous opaque layer structures may be configured as capacitive structures.

Abstract: Stacked layers of non-continuous opaque layer structures are disclosed herein that may be configured to block radiation such as visible light or other forms of light, while at the same time allowing penetration of ambient gases. In one example, such non-continuous opaque layer structures may be configured as stacked non-continuous metal layer structures that together fully block penetration of radiation while at the same provide sufficient open spaces between and/or within the metal layer segments of a given integrated circuit layer to meet maximum metal spacing rules. In another example, such non-continuous opaque layer structures may be configured as capacitive structures.

Abstract: A voltage reference generator has been discovered that generates a stable reference voltage that is less than the bandgap voltage of silicon for power supply voltages less than 2V, yet provides sufficient voltage headroom to operate a cascaded current mirror. In one embodiment, the voltage reference generator has a power supply rejection ratio of at least 60 dB and has improved noise performance as compared to traditional bandgap circuits. These advantages are achieved by leveraging the low-beta effect of a CMOS bipolar transistor to generate a current proportional to an absolute temperature.

Abstract: A voltage reference generator generates a stable reference voltage that is less than the bandgap voltage of silicon for power supply voltages less than 2V, yet provides sufficient voltage headroom to operate a current mirror. In one embodiment, the voltage reference generator has a power supply rejection ratio of at least 60 dB and has comparable noise performance as compared to traditional bandgap cirucits. These advantages are achieved by subtracting a current proportional to a complement of an absolute temperature from a current proportional to the absolute temperature to generate a voltage having a positive temperature coefficient, which is then added to a voltage that is a complement of the absolute temperature to achieve a voltage that has a low temperature coefficient.

Abstract: An output buffer circuit drives multiple signal formats. The output buffer circuit reduces duplication of output bond pads on an integrated circuit die. The output buffer circuit reduces a need for including conversion buffers on system boards. A single integrated circuit including the output buffer circuit may meet a variety of applications. The output buffer achieves these results with a programmable output voltage swing and a programmable output common mode voltage. In some embodiments of the present invention, an integrated circuit includes at least one single-ended buffer and at least one differential circuit coupled to a pair of outputs. One of the single-ended buffer and the differential circuit is selectively enabled to provide a signal to the outputs.

Abstract: An analog to digital converter system includes first and second delta sigma converters, a calculation engine, and a serial interface on a single chip. The calculation engine is configured to calculate energy, power, rms current and voltage for single phase 2 or 3 wire power meters. Voltage and current are measured with a shunt or transformer, and a divider or transformer, respectively. The serial interface is bidirectional for communication with a microprocessor or controller, and provides a fixed width programmable frequency output proportional to energy. The digital converter system is user system calibratible.

Abstract: A capacitively isolated input system that permits sensing of an input voltage with a below-ground value or a below-substrate voltage value. Multiple input signals are received, and each input signal is connected to cross-connected switching components. Switched output signals are capacitively connected to additional switching components and to a sensing amplifier. This system allows the sensing amplifier to receive capacitively isolated input signals and to provide corresponding output signals at voltages no lower than ground voltage.

Abstract: A self-timed multiplier and method are disclosed together with an analog to digital converter (ADC), which reduces ADC latency without requiring large silicon areas for implementation. The self-timed multiplier may be utilized by delta-sigma ADCs to perform gain compensation multiplications at the end of convolution, or may be used by other ADC designs or ADC systems for multiplications required during each convolution. The self-timed multiplier utilizes cascaded adders that produce completion signals to isolate the operation of the self-timed multiplier from the system clock of the ADC. The multiplier disclosed provides a self-timed, asynchronous circuit that will complete the desired multiplication in the time it takes for the required additions to propagate through the cascaded adders.

Abstract: A system and method for providing a dc accurate multi-rate digital filter with common coefficient set and dc gain correction utilizes at least one common coefficient set and at least one dc gain correction factor to provide a variable, dc accurate and corrected, multi-rate, digital filter using dc gain corrected subsets of the one stored common coefficient set. The filter maintains at least one common digital filter coefficient set which includes a number of coefficient values.

Abstract: A novel serial port interface system and method are disclosed. The serial port interface system achieves a three-pin interface mode with only a serial data input pin, a serial data output pin, and a serial clock pin by allocating a bit in an on-chip register to identify a three-pin conversion-done mode. In this three-pin mode, the serial data output pin signals an external device that data is ready to be accessed. Also disclosed with this three-pin conversion-done mode is a single conversion data read and a continuous conversion data read that may be selected through two separate bits in an on-chip register. In another aspect, a multiple register access capability is disclosed that allows multiple on-chip registers to be accessed with a single read/write command. This is accomplished by allocating a register select address in a command register to identify a group of registers, such as all of the set-up registers (gain, offset and configuration).

Abstract: An oversampling analog-to-digital modulator includes an analog loop filter which has a first integrator stage which operates as a continuous time integrator. the second, third, and fourth integrator stages are discrete time or sampling integrators. The continuous time first integrator provides the required thermal noise characteristics of the loop filter while the discrete time integrator stages provide loop stability and transfer characteristics which are advantageous to the overall operation of the analog-to-digital modulator.

Abstract: An oversampling analog-to-digital modulator includes an analog loop filter which has a first integrator stage which is a single-ended integrator. The second, third, and fourth integrator stages are fully-differential integrators. The first integrator provides the required thermal noise characteristics of the loop filter with only one feedback capacitor which is external to the integrated circuit chip, while the fully-differential integrator stages provide improved suppression of charge injection transients.

Abstract: A chopper stabilized analog-to-digital converter includes an analog modulator (10) and a digital filter (12). The analog modulator (10) is comprised of four integrators, a first integrator (20) which is continuous time and the remaining stages of integration (22) which are either continuous or discrete. The first integrator (20) is a chopper stabilized integrator which is comprised of a chopper stabilized differential amplifier (32) which has a single ended output and operates in a continuous time mode. The modulator has a zero that is located at the harmonics of the sampling frequency of the modulator and the chopping clock for the chopper stabilized operation operates at the sampling frequency.

Abstract: An oscillation detect and reset circuit is provided for an analog modulator that includes a first stage of integration having a single ended differential amplifier (32) which is connected to the input of three stages of subsequent integration (40), (42) and (44), in a cascaded configuration. The output of the last stage of integration (44) is connected to the input of a one-bit quantizer (48). The output of the one-bit quantizer (48) is connected to the input of a current (50) feedback, which is connected between a summing node (36) and a negative voltage supply. The summing node (36) sums the current feedback with an input voltage for input to the amplifier (32). Switches (52), (54) and (56) are provided across the inputs and outputs of the integration stages (40), (42) and (44), respectively. The sensing of an unstable condition on the output of second stage of integration (40) is detected by oscillation detect comparators (60) and (62) to initiate a count cycle in a five-bit counter (66).