Patents by Inventor Bruce Pember

Bruce Pember has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6360353
    Abstract: Disclosed are methods and computer readable media containing program instructions for testing alternating current characteristics of a computer model of an integrated circuit design. The testing implements an associated AVF file and an associated DUT file for the integrated circuit design.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: March 19, 2002
    Assignee: Adaptec, Inc.
    Inventors: Bruce Pember, Christine Odero, Honda Yang
  • Patent number: 6304837
    Abstract: Disclosed is a method for generating AVF test file data for use in testing a simulation of an integrated circuit design, and verifying the generated AVF test file data before they are delivered to a physical silicon version of the integrated circuit design. The generation method includes providing a map file that contains a plurality of identifying statements for each multiple port I/O cell (or also including single port I/O cells) in the integrated circuit design. Then, generate a verilog executable file for the integrated circuit design. The verilog executable file is configured to contain data associated with the map file, a netlist of the integrated circuit design, output enable data derived from the netlist, and AVF data conversion information. The method further comprises executing the verilog executable file along with a test bench that includes the netlist of the integrated circuit design, a set of test files, and models.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: October 16, 2001
    Assignee: Adaptec, Inc.
    Inventors: Thomas Kennith Geiger, Honda Yang, Bruce Pember
  • Patent number: 6212656
    Abstract: A method of configuring scan mode circuitry of an integrated circuit (IC) device includes parsing through an initial file of the scan-flops that are to be included in the scan mode circuitry. The initial file can be prepared with a synthesis tool such as Synopsys. A particular subset of scan-flops are parsed, according to an identified number to be included in each scan chain. A holding tank is created to hold each subset of scan-flops for each scan chain. Each holding tank is then used to form a scan path and to stitch the corresponding scan chain. The parsing of the scan-flops into holding tanks can be performed with a c-shell script. Also, the c-shell script can be called by a Synopsys dc_shell script.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: April 3, 2001
    Assignee: Adaptec, Inc.
    Inventors: Brian Thomas Fosco, Bruce Pember