Abstract: Systems and methods that allow for dynamically deconfiguring, reconfiguring and/or otherwise configuring nodes (e.g., processors) in a symmetric multiprocessing system (e.g., a symmetric multiprocessor) in a manner that avoids, or at least limits, inefficiencies such as renumbering of node IDs, system reboots, SW configuration handle changes, and the like. In one arrangement, a number of modules, tables and/or the like that are configured to generate node IDs and/or convert node IDs from one form to another form can be intelligently implemented within an SMP to allow the various processes and/or components of an SMP to utilize the node IDs in a more efficient manner. For instance, as SDs in an SMP are often configured to work with CNIDs (e.g., for use in determining at which node a particular requested cache line resides), any node GNIDs that are sent to the SD for processing can first be converted into corresponding CNIDs.

Abstract: Systems and methods that allow for dynamically deconfiguring, reconfiguring and/or otherwise configuring nodes (e.g., processors) in a symmetric multiprocessing system (e.g., a symmetric multiprocessor) in a manner that avoids, or at least limits, inefficiencies such as renumbering of node IDs, system reboots, SW configuration handle changes, and the like. In one arrangement, a number of modules, tables and/or the like that are configured to generate node IDs and/or convert node IDs from one form to another form can be intelligently implemented within an SMP to allow the various processes and/or components of an SMP to utilize the node IDs in a more efficient manner. For instance, as SDs in an SMP are often configured to work with CNIDs (e.g., for use in determining at which node a particular requested cache line resides), any node GNIDs that are sent to the SD for processing can first be converted into corresponding CNIDs.

Abstract: A system may be employed for allowing the synchronous operation of an asynchronous system. The system may be a system that may include multiple clusters. The clusters may include asynchronous clock domains and may also receive a global clock signal through a global clock grid that may overlay the system. Furthermore, a method may be employed for synchronizing asynchronous clock domains within a cluster. The method of synchronizing may include providing a global clock that corresponds to a global clock grid to each cluster. Additionally, the method of synchronizing may include accounting for the mismatch between the asynchronous clock domains by employing logic in a block.

Abstract: Methods and apparatuses are presented that allow power savings on a processor executing a plurality of threads on a plurality of cores. The method may include providing a first timing signal to a processor, determining the power requirements of the processor, loading a symbol into a shift register, where the symbol may be associated with the power requirements of the processor, providing a second timing signal to the processor, where the second timing signal may include a gated representation of the first timing signal and the symbol.

Abstract: Methods and apparatuses are presented that allow power savings on a processor executing a plurality of threads on a plurality of cores. The method may include providing a first timing signal to a processor, determining the power requirements of the processor, loading a symbol into a shift register, where the symbol may be associated with the power requirements of the processor, providing a second timing signal to the processor, where the second timing signal may include a gated representation of the first timing signal and the symbol.

Abstract: A system may be employed for allowing the synchronous operation of an asynchronous system. The system may be a system that may include multiple clusters. The clusters may include asynchronous clock domains and may also receive a global clock signal through a global clock grid that may overlay the system. Furthermore, a method may be employed for synchronizing asynchronous clock domains within a cluster. The method of synchronizing may include providing a global clock that corresponds to a global clock grid to each cluster. Additionally, the method of synchronizing may include accounting for the mismatch between the asynchronous clock domains by employing logic in a block.

Abstract: Embodiments of the present invention provide a stack renaming method and apparatus for stack based processors. Using principles of the present invention, a stack can be accessed simultaneously by one or more functional units in a stack processor. The stack apparatus includes a stack renaming unit capable of renaming a logical stack address to a real stack address. Each logical stack address corresponds to a storage element in the stack renaming unit which stores a real stack address. A circular counter is used in the stack renaming unit to sequentially cycle through each of the logical stack addresses. The real stack addresses corresponding to each of the logical stack addresses can be stored out of order in the stack renaming unit. A stack control unit is coupled to the stack renaming unit and provides one or more control signals to the stack renaming unit and coordinates the operation of the stack renaming unit within the stack apparatus.

Abstract: An apparatus for processing a write miss signal from a copy-back data cache includes a load-store unit with an allocating load buffer, a non-allocating store buffer, and a priority control circuit to generate write-after-read hazards and read-after-write hazards to preserve the processing priority of entries within the allocating load buffer and the non-allocating store buffer. A prefetch circuit enqueues a prefetch command in the allocating load buffer and a store command in the non-allocating store buffer upon a write miss to the copy-back data cache. Thus, the priority control circuit forces a write-after-read hazard on the store command in the non-allocating store buffer. As a result, the prefetch command in the allocating load buffer secures an allocated line in the copy-back data cache, allowing the store command of the non-allocating store buffer to write data to the allocated line.

Abstract: An innovative method and system of performing multiway branch operations on a microprocessor architecture which supports single instruction multiple data (SIMD) operations is provided. A computer processor includes a branch condition register, a graphic status register, a displacement register, a branch offset register, a program counter register and circuit logic responsive to a multiway branch opcode. Bitwise AND logic coupled to the branch condition register and the graphic status register performs a bitwise logical AND between a mask contained in the branch condition register and multiple comparison results contained in the graphic status register. An output port from bitwise logical AND is coupled to a constant array and selects a set of constant values based on the bitwise logical AND result value.