Patents by Inventor Bruce Porth

Bruce Porth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230307321
    Abstract: Structures for a through-silicon via and methods of forming a structure for a through-silicon via. The structure includes a substrate having a trench and surfaces that border the trench. The structure further includes a through-silicon via having a layer inside the trench. The layer is in direct contact with the surfaces of the substrate.
    Type: Application
    Filed: March 28, 2022
    Publication date: September 28, 2023
    Inventors: David Thomas, Cody Soule, John G. Twombly, Michael Brigham, Bruce Porth, Vivekanand Kalaparthi
  • Publication number: 20070287275
    Abstract: A method of fabricating polysilicon lines and polysilicon gates, the method of including: forming a dielectric layer on a top surface of a substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species essentially contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.
    Type: Application
    Filed: August 8, 2007
    Publication date: December 13, 2007
    Inventors: James Adkisson, John Ellis-Monaghan, Glenn MacDougall, Dale Martin, Kirk Peterson, Bruce Porth
  • Publication number: 20060275978
    Abstract: A semiconductor structure. The structure includes (a) a semiconductor substrate; (b) a hard mask layer on top of the semiconductor substrate; and (c) a hard mask layer opening in the hard mask layer. The semiconductor substrate is exposed to the atmosphere through the hard mask layer opening. The hard mask layer opening comprises a top portion and a bottom portion, wherein the bottom portion is disposed between the top portion and the semiconductor substrate. The bottom portion has a greater lateral width than the top portion.
    Type: Application
    Filed: July 20, 2006
    Publication date: December 7, 2006
    Inventors: June Cline, Dinh Dang, Mark Lagerquist, Jeffrey Maling, Lisa Ninomiya, Bruce Porth, Steven Shank, Jessica Trapasso
  • Publication number: 20060081556
    Abstract: A method for etching a deep trench in a semiconductor substrate. The method comprises the steps of (a) forming a hard mask layer on top of the semiconductor substrate, (b) etching a hard mask opening in the hard mask layer so as to expose the semiconductor substrate to the atmosphere through the hard mask layer opening, wherein the step of etching the hard mask opening includes the step of etching a bottom portion of the hard mask opening such that a side wall of the bottom portion of the hard mask opening is substantially vertical, and (c) etching a deep trench in the substrate via the hard mask opening.
    Type: Application
    Filed: October 15, 2004
    Publication date: April 20, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: June Cline, Dinh Dang, Mark Lagerquist, Jeffrey Maling, Lisa Ninomiya, Bruce Porth, Steven Shank, Jessica Trapasso
  • Publication number: 20060073689
    Abstract: A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.
    Type: Application
    Filed: October 4, 2004
    Publication date: April 6, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Adkisson, John Ellis-Monaghan, Glenn MacDougall, Dale Martin, Kirk Peterson, Bruce Porth
  • Publication number: 20060063326
    Abstract: A method of forming a structure, an array of structures and a memory cell, the method of fabricating a structure, including: (a) forming a trench in a substrate; (b) depositing a first layer of polysilicon on a surface of the substrate, the first layer of polysilicon filling the trench; (c) chemical-mechanical-polishing the first layer of polysilicon at a first temperature to expose the surface of the substrate; (d) removing an upper portion of the first polysilicon from the trench; (e) depositing a second layer of polysilicon on the surface of the substrate, the second layer of polysilicon filling the trench; and (f) chemical-mechanical-polishing the second layer of polysilicon at a second temperature to expose the surface of the substrate, the second temperature different from the first temperature.
    Type: Application
    Filed: July 23, 2004
    Publication date: March 23, 2006
    Applicant: International Business Machines Corporation
    Inventors: Garth Brooks, Bruce Porth, Steven Shank, Eric White