Abstract: A detector circuit utilizing two comparators, the first of which initially switches output at a first bias level, and the second of which switches output responsive to a preselected voltage on a capacitor. The voltage on the capacitor is controlled by the output of the first comparator which charges and discharges it through a dual time constant arrangement in order to sensitize the detector to activate a recorder after a preselected delay only upon receipt of a particularly shaped long duty cycle input signal. After receipt of the input signal, the bias level of the first comparator is changed so as to prevent switching until receipt of a second preselected input signal. In addition, after receipt of the first input signal, the time constant of charge-discharge arrangement for the capacitor is again altered.