Abstract: An adapter module executing on a computing device of a computing environment is to be used to transmit packets from a network interface card of the computing environment to a control program executing within the computing environment. The adapter module obtains packet information of a packet received at the network interface card. Based on obtaining the packet information, a packet completion queue entry is generated in a packet completion queue and the packet information is stored in the packet completion queue entry. The packet information is to be used to locate a data buffer into which the packet is stored. The packet completion queue entry is provided to the control program to be used by the control program to retrieve the packet from the data buffer.

Abstract: An adapter module executing on a computing device of a computing environment is to be used to transmit packets from a network interface card of the computing environment to a control program executing within the computing environment. The adapter module obtains packet information of a packet received at the network interface card. Based on obtaining the packet information, a packet completion queue entry is generated in a packet completion queue and the packet information is stored in the packet completion queue entry. The packet information is to be used to locate a data buffer into which the packet is stored. The packet completion queue entry is provided to the control program to be used by the control program to retrieve the packet from the data buffer.

Abstract: An instruction executing within a computing environment is used to perform at least one operation on one or more controls of a queue to be used in communications between a control program executing within the computing environment and an adapter module of the computing environment. Execution of the instruction includes obtaining an indication of the queue for which at least one operation is to be performed on the one or more controls of the queue. At least one operation is performed on the one or more controls of the queue and a result of executing the instruction is provided.

Abstract: A control program executing on a computing device of a computing environment transmits control request information to an adapter module executing within the computing environment. The transmitting uses a control plane transmit queue of a set of queues. The control plane transmit queue identifies a location to store the control request information to be retrieved by the adapter module. The control program receives from the adapter module an indication of another location storing control reply information replying to the control request information. The indication is obtained from a control plane receive queue of the set of queues. The control program retrieves from the another location the control reply information and performs processing based on the control reply information.

Abstract: Embodiments of the present disclosure implement hardware-based snoop logic streaming timers for input/output (I/O) communications between a host and a shared network adapter in a computing system. The disclosed embodiments describe a hardware-based snoop logic and snoop logic timer function control of input/output (I/O) processor monitoring a defined memory area to detect a completion queue entry being written to a completion queue, and implementing streaming timers and interpacket timers, based on the completion queue entry and predefined configuration information for an associated host interface connection, to provide streaming data status, interpacket arrival times, and streaming timer expiration for the associated host interface connection.

Abstract: Embodiments of the present disclosure implement hardware-based snoop logic streaming timers for input/output (I/O) communications between a host and a shared network adapter in a computing system. The disclosed embodiments describe a hardware-based snoop logic and snoop logic timer function control of input/output (I/O) processor monitoring a defined memory area to detect a completion queue entry being written to a completion queue, and implementing streaming timers and interpacket timers, based on the completion queue entry and predefined configuration information for an associated host interface connection, to provide streaming data status, interpacket arrival times, and streaming timer expiration for the associated host interface connection.

Abstract: The embodiments herein describe communication between a host and a shared network adapter. Control queues can be activated first in order to issue control commands to configure the data plane in the shared network adapter. If an error occurs, the system can suspend the data queues while permitting the control queues to still transmit control plane data between the host and the shared network adapter.

Abstract: Embodiments herein describe techniques for providing interrupts from a shared network adapter to a host operating system or control program. A register can store an interrupt state of the host that indicates whether an interrupt is required. For example, the host may still be busy processed previous received data (e.g., a packet received from a network), which means no interrupt is required. When the host has processed each of the requests from the shared network adapter, the interrupt state in the register can be changed that if any additional data is received, an interrupt is required. Moreover, the register can include a bitmask to indicate which of a plurality of receive data queues has data ready for the host to process.

Abstract: Systems and techniques for snooping input/output (I/O) events in a computing system are described. An example technique includes obtaining a configuration comprising a plurality of snoop space profiles, each snoop space profile indicating a respective range of memory addresses that map to a respective completion queue. The technique also includes monitoring input/output (I/O) traffic exchanged across a communication interface between an I/O adapter and a processor in a computing system, based on the configuration. The technique further includes performing one or more actions to assist processing of the I/O traffic, based in part on the monitoring.

Abstract: Embodiments herein describe techniques for a host to provide TX packets to a shared adapter that then uses a NIC to forward the TX packet to a network. In one embodiment, the host creates or fills in one or more TX storage block page entries (SBPE) for the TX packet and stores an index of the TX SBPE in host memory. The host memory can also store an initiative state that tracks whether the shared adapter is currently processing TX packets. If not, the host can issue an interrupt to the shared adapter, along with the index associated with the TX SBPE. The shared adapter can then fetch the TX SBPE from host memory and program the NIC to transmit the TX packet.

Abstract: Embodiments herein describe techniques for establishing data constructs for a data device that enable communication between a host and a shared adapter. A shared adapter facilitates communication with one or more hosts coupled to a NIC. To do so, a host can establish the data device in each operating system that wishes to communicate with the shared adapter. This can include establishing data constructs such as storage block pages, queue indexes, and interrupt registers in the host memory. The host can then transmit a queue description record (QDR) to the shared adapter so the adapter can configure the queues and has the addresses of the data constructs in the host memory.

Abstract: The embodiments herein describe configuring a data device that enables communication between a host and a shared network adapter. The data device can include data connections between the host and the shared network adapter. The data device can have both control queues in a control plane and data queues in a data plane. The control queues can be activated first in order to issue control commands to configure the data plane in the shared network adapter.

Abstract: In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.

Abstract: In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Abstract: In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.

Abstract: In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.