Abstract: In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.

Abstract: In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Abstract: In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.

Abstract: In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.

Abstract: Examples of techniques for packet flow tracing in a parallel processor complex are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include receiving, at the parallel processor complex, a task to be executed by the parallel processor complex, wherein the parallel processor complex comprises a trace processor and a plurality of task execution processors; creating, by the trace processor, a trace entry by allocating an element from a shared queue; loading, by the trace processor, the trace entry into a common trace buffer; and loading, by the trace processor, the trace entry into a host interface/queue pair index trace buffer.

Abstract: Examples of techniques for packet flow tracing in a parallel processor complex are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include receiving, at the parallel processor complex, a task to be executed by the parallel processor complex, wherein the parallel processor complex comprises a trace processor and a plurality of task execution processors; creating, by the trace processor, a trace entry by allocating an element from a shared queue; loading, by the trace processor, the trace entry into a common trace buffer; and loading, by the trace processor, the trace entry into a host interface/queue pair index trace buffer.

Abstract: A physical host executes a virtual machine monitor (VMM) that instantiates a source virtual machine (VM). In response to the VMM receiving from the source VM a packet specifying a first destination address of a destination VM and a second destination address of a default gateway, the VMM determines whether the packet can be communicated to the destination VM without the packet being routed by the default gateway. In response to the VMM determining that the packet can be communicated to the destination VM without the packet being routed by the default gateway, the VMM forwards the packet to the destination VM such that the packet bypasses routing by the default gateway.

Abstract: A physical host executes a virtual machine monitor (VMM) that instantiates a source virtual machine (VM). In response to the VMM receiving from the source VM a packet specifying a first destination address of a destination VM and a second destination address of a default gateway, the VMM determines whether the packet can be communicated to the destination VM without the packet being routed by the default gateway. In response to the VMM determining that the packet can be communicated to the destination VM without the packet being routed by the default gateway, the VMM forwards the packet to the destination VM such that the packet bypasses routing by the default gateway.

Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.

Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.

Abstract: Examples of techniques for packet flow tracing in a parallel processor complex are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include receiving, at the parallel processor complex, a task to be executed by the parallel processor complex, wherein the parallel processor complex comprises a trace processor and a plurality of task execution processors; creating, by the trace processor, a trace entry by allocating an element from a shared queue; loading, by the trace processor, the trace entry into a common trace buffer; and loading, by the trace processor, the trace entry into a host interface/queue pair index trace buffer.

Abstract: Examples of techniques for packet flow tracing in a parallel processor complex are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include receiving, at the parallel processor complex, a task to be executed by the parallel processor complex, wherein the parallel processor complex comprises a trace processor and a plurality of task execution processors; creating, by the trace processor, a trace entry by allocating an element from a shared queue; loading, by the trace processor, the trace entry into a common trace buffer; and loading, by the trace processor, the trace entry into a host interface/queue pair index trace buffer.

Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.

Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.

Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.

Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.