Abstract: An exponentiation circuit for computing an exponential power of a finite field element includes combinatory logic circuits that map input digits of a multi-digit field element ? to output digits of an output multi-digit field element ?2m. The exponentiation circuit is capable of computing a power of a field element without performing any multiplication operations and requires only exclusive-OR logic operations to generate the output exponential field element. A circuit for generating a multiplicative inverse of a finite field element can be constructed from a set of parallel exponentiation circuits, with each of the parallel exponentiation circuits generating a different multi-digit field element ?2m directly from the input field element ?. Multiplier circuits multiply together the outputs of the parallel exponentiation circuits to generate the multiplicative inverse of the field element ?.

Abstract: An exponentiation circuit for computing an exponential power of a finite field element includes combinatory logic circuits that map input digits of a multi-digit field element P to output digits of an output multi-digit field element ?2m. The exponentiation circuit is capable of computing a power of a field element without performing any multiplication operations and requires only exclusive-OR logic operations to generate the output exponential field element. A circuit for generating a multiplicative inverse of a finite field element can be constructed from a set of parallel exponentiation circuits, with each of the parallel exponentiation circuits generating a different multi-digit field element ?2m directly from the input field element ?. Multiplier circuits multiply together the outputs of the parallel exponentiation circuits to generate the multiplicative inverse of the field element ?.

Abstract: A programmable application specific integrated circuit (ASIC) for implementing operations that involve a plurality of computational functions. The programmable ASIC comprises a plurality of fixed functions and programmable switch logic. Each of the plurality of fixed functions is parameterized such that its operational characteristics are programmable using different operating parameters. In addition, each of the plurality of fixed functions inputs and outputs data in accordance with common interface rules. The programmable switch logic is configurable to link two or more of the fixed functions in a sequence to perform desired operations. The fixed functions are implemented using “hard” or fixed digital logic gates such as those in an ASIC.