Abstract: A processor is described which is particularly useful in a cell which cell forms part of a network for sensing, communicating and controlling. The processor includes a plurality of sets of registers, each associated with a different processor. Each set of registers shares a single ALU. Data associated with each set of registers is simultaneously moved through a path which includes the registers, ALU, and memory.

Abstract: An interface apparatus between a video tape recorder and a disc drive having a non-removable magnetic storage medium and a controller is disclosed. The video tape recorder provides memory back-up to data stored on the disc drive. The interface apparatus comprises a data bus for transferring the data between a shift register in the interface to the controller of the disc drive. The shift register transforms the parallel data from the controller to serial data when data is being written onto the VTR, and transforms the serial data from the VTR to parallel format when data is being read into the disc drive. The interface appartus has a clock for generating video signals. In addition, a circuit separates the sync and data portions of the video signal when the video signal is read from the tape of the VTR into the controller. A CRC generator checks for errors in the transmission of data to and from the video tape recorder.