Patents by Inventor Bruce T. Holden

Bruce T. Holden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Gate metallization methods for self-aligned sidewall gate GaN HEMT
    Patent number: 8698201
    Abstract: A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer and a barrier layer over the channel layer includes forming a gate of a first dielectric, forming first sidewalls of a second dielectric on either side and adjacent to the gate, selectively etching into the buffer layer to form a mesa for the field effect transistor, depositing a dielectric layer over the mesa, planarizing the dielectric layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the dielectric layer over the mesa are on the same planarized surface, depositing metal on the planzarized surface, annealing to form the gate into a metal silicided gate, and etching to remove excess non-silicided metal.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: April 15, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Dean C. Regan, Keisuke Shinohara, Andrea Corrion, Ivan Milosavljevic, Miroslav Micovic, Peter J. Willadsen, Colleen M. Butler, Hector L. Bracamontes, Bruce T. Holden, David T. Chang
  • Gate metallization methods for self-aligned sidewall gate GaN HEMT
    Patent number: 8558281
    Abstract: A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer and a barrier layer over the channel layer includes forming a gate including silicon, forming first sidewalls of a first material on either side and adjacent to the gate, selectively etching into the buffer layer to form a mesa for the field effect transistor, depositing a material layer over the mesa, planarizing the material layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the material layer over the mesa are on the same planarized surface, depositing metal on the planzarized surface, annealing to form the gate into a metal silicided gate, and etching to remove excess non-silicided metal.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: October 15, 2013
    Assignee: HRL Laboratories, LLC
    Inventors: Dean C. Regan, Keisuke Shinohara, Andrea Corrion, Ivan Milosavljevic, Miroslav Micovic, Peter J. Willadsen, Colleen M. Butler, Hector L. Bracamontes, Bruce T. Holden, David T. Chang