Abstract: A digital analyzer for a laser velocimeter which compresses data into groups for a histogram display. A data processor containing the velocimeter information is fed through a multiplexer to a memory which is controlled by a data interrupt circuit that is fed by a two-phase clock. One phase of the clock pulses an address counter which feeds the multiplexer and a first digital-to-analog converter that controls the x-drive of a cathode ray tube. The data processor also has an output fed to a full adder and then fed back to the memory with the same output being fed to a storage register followed by a second digital-to-analog converter that controls the y-drive of the cathode ray tube.