Abstract: A method includes designating a first sampling phase for a signal captured from a magnetic storage medium, where the signal is representative of information stored by the magnetic storage medium. The method further includes capturing a first waveform associated with the signal at the first sampling phase. The method also includes designating a second sampling phase different from the first sampling phase for the signal. The method further includes capturing a second waveform associated with the signal at the second sampling phase. The method also includes interleaving the first waveform and the second waveform to form an oversampled waveform. The first waveform and the second waveform are captured at a rate at least substantially equal to a rate at which the information stored by the magnetic storage medium was written to the magnetic storage medium.

Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.

Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.

Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.

Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.

Abstract: Tracking percent overload signal as an indicator of output signal magnitude is achieved by measuring the percent of time the envelope of a varying modulated signal is above a predetermined programmable threshold. The technique is implemented by a level detector including an envelope detector along with circuitry for detecting when the envelope has exceeded the programmable threshold. The output of the level detector is sampled and fed to a counter which provides a digital output which indicates the percentage of time the envelope exceeds the set threshold.

Abstract: A bandgap voltage reference circuit for 0.35-.mu.m, 3-volt CMOS technology operates in an essentially temperature independent manner and having low supply voltages. The bandgap voltage reference circuit incorporates two operational amplifiers. One operational amplifier biases bipolar devices of the circuit and generates a PTAT voltage across a resistor, and the other operational amplifier buffers a voltage related to the PTAT voltage and a voltage across one bipolar device to generate the bandgap voltage reference. In one embodiment, the circuit includes a start-up circuit to ensure a stable and desired start-up state. A current bias may also be provided. The bandgap voltage reference of the second operational amplifier may also provide a regulated supply for the first stage of the circuit. The second operational amplifier also provides a buffered output to a resistor divider circuit to supply a voltage divider to generate voltages below the 1.24-volt bandgap voltage.

Abstract: This is an improved resistive line battery feed circuit where the improvement consists in establishing a balanced stable power point using an opamp and capacitive input and feeding the AC output to both lines of the tip and ring circuit via opamps and a hybrid for injecting current. In this manner longitudinal balance is maintained. Current is added to the line circuit by a modulated DC current source.