Abstract: Disclosed are a method and system for measuring the performance of individual logical partitions of a logically partitioned computer system. Preferably, the method and system both hardware and firmware to allow measurement samples to be collected only for user specified zones of interest. In one embodiment, the method comprises the steps of specifying a Zone or Zones of interest (a Zone being a logical partition), collecting measurement samples only from the one or more specified Zones of interest, and measuring the performance of each of these Zones using only the measurement samples collected from said each of the Zones.

Abstract: The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a lookaside buffer for some higher level address translation levels, and the second sub-unit comprising a lookaside buffer for some lower level address translation levels, and said second sub-unit being arranged to store TLB index address information of the upper level sub-unit as tag information in its lower level TLB structure, comprising the steps of collecting intermediate address translation results on different virtual machine levels; and buffering the intermediate translation results in the translation lookaside buffer.

Abstract: The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a lookaside buffer for some higher level address translation levels, and the second sub-unit comprising a lookaside buffer for some lower level address translation levels, and said second sub-unit being arranged to store TLB index address information of the upper level sub-unit as tag information in its lower level TLB structure, comprising the steps of collecting intermediate address translation results on different virtual machine levels; and buffering the intermediate translation results in the translation lookaside buffer.

Abstract: A dual system shared cache directory structure for a cache memory performs the role of an inclusive shared system cache, i.e., data, and system control, i.e., coherency. The system includes two separate system cache directories in the shared system cache. The two separate cache directories are substantially equal in size and collectively large enough to contain all of the processor cache directory entries, but with only one of these separate cache directories hosting system-cache data to back the most recent fraction of data accessed by the processors. The other cache directory retains only addresses, including addresses of lines LRUed out from the first cache directory and the identity of the processor using the data. Thus by this expedient, only the directory known to be backed by system cached data will be evaluated for system cache memory data.

Abstract: Buffered indexing for a computer's array such as a cache is used to synchronize parent entries with children and allow background invalidation (that is, suspending the invalidation should a new request of the array come in, resuming the invalidation after the request is satisfied) of the child entries. A method for synchronization uses linking of (multiple) entries in lower-level tables to single entries in a higher-level table with a buffered index value. This index value increments each time the higher-level entry is replaced or invalidated (and thus disassociated with its corresponding lower-level entries). Multiple sets of index values are maintained, so that when one set is exhausted, processing can continue with one of the other sets. All corresponding lower-level entries with index values from the old (dirty) set can then be scrubbed (invalidated) while new entries are built from the new (clean) set.

Abstract: Disclosed are a method and system for measuring the performance of individual logical partitions of a logically partitioned computer system. Preferably, the method and system both hardware and firmware to allow measurement samples to be collected only for user specified zones of interest. In one embodiment, the method comprises the steps of specifying a Zone or Zones of interest (a Zone being a logical partition), collecting measurement samples only from the one or more specified Zones of interest, and measuring the performance of each of these Zones using only the measurement samples collected from said each of the Zones.

Abstract: Buffered indexing for a computer's array such as a cache is used to synchronize parent entries with children and allow background invalidation (that is, suspending the invalidation should a new request of the array come in, resuming the invalidation after the request is satisfied) of the child entries. A method for synchronization uses linking of (multiple) entries in lower-level tables to single entries in a higher-level table with a buffered index value. This index value increments each time the higher-level entry is replaced or invalidated (and thus disassociated with its corresponding lower-level entries). Multiple sets of index values are maintained, so that when one set is exhausted, processing can continue with one of the other sets. All corresponding lower-level entries with index values from the old (dirty) set can then be scrubbed (invalidated) while new entries are built from the new (clean) set.

Abstract: The system and method described herein is a dual system directory structure that performs the role of system cache, i.e., data, and system control, i.e., coherency. The system includes two system cache directories. These two cache directories are equal in size and collectively large enough to contain all of the processor cache directory entries, but with only one of these cache directories hosting system-cache data to back the most recent fraction of data accessed by the processors, and the other cache directory retains only addreses, including addresses of lines LRUed out and the processor using the data. By this expedient, only the directory known to be backed by system cached data will be evaluated for system cache data hits.

Abstract: A method and apparatus for implementing a combined data/coherency cache for a shared memory multi-processor. The combined data/coherency cache includes a system cache with a number of entries. The method includes building a system cache directory with a number of entries equal to the number of entries of the system cache. The building includes designating a number of sub-entries for each entry which is determined by a number of sub-entries operable for performing system cache coherency functions. The building also includes providing a sub-entry logic designator for each entry, and mapping one of the sub-entries for each entry to the system cache via the sub-entry logic designator.

Abstract: A method, system, and computer program product for implementing a dual-addressable cache is provided. The method includes adding fields for indirect indices to each congruence class provided in a cache directory. The cache directory is indexed by primary addresses. In response to a request for a primary address based upon a known secondary address corresponding to the primary address, the method also includes generating an index for the secondary address, and inserting or updating one of the indirect indices into one of the fields for a congruence class relating to the secondary address. The indirect index is assigned a value of a virtual index corresponding to the primary address. The method further includes searching congruence classes of each of the indirect indices for the secondary address.