Abstract: Incorporation of a sensor, such as an optical or laser based sensor, into a wafer edge processing unit, such as a WEE unit or mechanism. This sensor enables the WEE unit to be referenced to the wafer edge. Specifically, the sensor can be used to place a WEE unit in a fixed but accurate location at the beginning of the wafer edge expose process. Another approach is to have the WEE drive controller actively follow the edge of the wafer as it rotates during the WEE process, which has the advantage of compensating for any wafer centering errors as well as diameter and placement errors. In yet another approach, the edge sensor is used to sense and track the edge of a previous layer WEE pattern. The sensor can also facilitate the measuring of a distance from a wafer edge to a WEE edge feature.

Abstract: An embodiment of the present invention provides a method to utilize data from many different die sizes and products so that highly detailed wafer profiles can be generated that have an improved signal to noise ratio and spatial resolution. Instead of being limited to single die size like normal wafer maps, this method takes advantage of multiple die sizes and their variation in placement on the wafer to increase the information available about the wafer patterns.

Abstract: A semiconductor chip is provided which includes active and inactive IP cores. The spaces on the metal layer associated with the inactive IP cores includes voltage contrast inspection structures. The voltage contrast inspection structures serve to provide improved planarization of the metal layer and provided improved inspection capabilities.

Abstract: An apparatus includes an edge expose unit for exposing an annular area in an edge exclusion zone of a wafer to radiation having a wavelength suitable for removing a film from the wafer in the annular area and a radiation modulator coupled to the edge expose unit for modulating the radiation to pattern the film in the annular area.

Abstract: A semiconductor chip is provided which includes active and inactive IP cores. The spaces on the metal layer associated with the inactive IP cores includes voltage contrast inspection structures. The voltage contrast inspection structures serve to provide improved planarization of the metal layer and provided improved inspection capabilities.

Abstract: A semiconductor chip is provided which includes active and inactive IP cores. The spaces on the metal layer associated with the inactive IP cores includes voltage contrast inspection structures. The voltage contrast inspection structures serve to provide improved planarization of the metal layer and provided improved inspection capabilities.

Abstract: A method of determining the distance from an edge feature to a wafer edge. The wafer is put onto an image acquisition tool, and images are captured and classified. Based on the coordinates of the images and their classifications, the distance between an edge feature and the wafer edge is determined. Reference marks can be etched into the wafer to facilitate the measurement. The measurement technique is objective, and can be used to minimize the edge exclusion ring as well as defects that originate from the edge of the wafer.

Abstract: A method of forming a carbon nanotube fuse by depositing a carbon nanotube layer, then depositing a cap layer directly over the carbon nanotube layer. The cap layer is formed of a material that has an insufficient amount of oxygen to significantly oxidize the carbon nanotube layer under operating conditions, and is otherwise sufficiently robust to protect the carbon nanotube layer from oxygen and plasmas. A photoresist layer is formed over the cap layer, and the photoresist layer is patterned to define a desired size of fuse. Both the cap layer and the carbon nanotube layer are completely etched, without removing the photoresist layer, to define the fuse having two ends in the carbon nanotube layer. Just the cap layer is etched, without removing the photoresist layer, so as to reduce the cap layer by a desired amount at the edges of the cap layer under the photoresist layer, without damaging the carbon nanotube layer.

Abstract: An apparatus includes an edge expose unit for exposing an annular area in an edge exclusion zone of a wafer to radiation having a wavelength suitable for removing a film from the wafer in the annular area and a radiation modulator coupled to the edge expose unit for modulating the radiation to pattern the film in the annular area.

Abstract: A method for selecting test site locations on a substrate, by a) specifying a subset of all test site locations on the substrate, and b) selecting a desired number of candidate test site locations from within the subset of test site locations on the substrate. c) While selecting one of the candidate test site locations and holding all others of the candidate test site locations as fixed, determining a new location for the selected one of the candidate test site locations, which new location increases a test sensitivity, as estimated by a trace of a variance-covariance matrix. d) Repeating step (c) for each candidate test site location in the subset of test site locations, to produce a finalized set of candidate test site locations, until a desired end point is attained.

Abstract: A method includes steps of: (a) providing a wafer on which a film has been deposited; (b) exposing an annular area in an edge exclusion zone of the wafer to radiation having a wavelength suitable for patterning the film in the annular area; and (c) modulating the radiation while exposing the annular area to form a pattern in the film in the annular area.

Abstract: A method includes steps of: (a) providing a wafer on which a film has been deposited; (b) exposing an annular area in an edge exclusion zone of the wafer to radiation having a wavelength suitable for patterning the film in the annular area; and (c) modulating the radiation while exposing the annular area to form a pattern in the film in the annular area.

Abstract: An apparatus for cleaning a substrate. A cleaning chamber contacts the substrate with a cleaning solution. The cleaning solution thereby removes contaminants from the substrate and additionally leaches material from the substrate. A gettering chamber receives the cleaning solution, and includes a surface for chemically attracting the leached material and precipitating the leached material at least in part out of the cleaning solution. By removing the leached copper from the cleaning solution In this manner, the various embodiments of the present invention reduce the amount of copper that is available for plating out of the solvent, and therefore reduces the number and size of nodules that can form on the substrate. Thus, the need for other expensive approaches, like chemical replacement or less effective cleaning solvents, is obviated.

Abstract: A method of removing an edge bead of a coated material on a substrate. The substrate is rotated, and a fluid that solvates the coated material is delivered. The delivery of the fluid is directed radially inward on the substrate at a rate of between about three millimeters per second and about twenty millimeters per second until a desired innermost fluid delivery position on the substrate is attained. Immediately upon attaining the desired innermost fluid delivery position on the substrate, the delivery of the fluid is directed radially outward off the substrate at a rate of more than zero millimeters per second and less than about four millimeters per second. The rotation of the substrate is ceased.

Abstract: A method for creating a reference for a first position on a substrate edge. A first reference point is selected relative to a circumference of the substrate edge, and a second reference point is selected relative to a bevel of the substrate edge. A first distance along the circumference of the substrate edge between the first reference point and the first position is identified as a first coordinate, and a second distance along the bevel of the substrate edge between the second reference point and the first position is identified as a second coordinate. The first coordinate and the second coordinate are used as the reference for the first position.

Abstract: A method of determining a cost effective number of corrective tests to perform on a process experiencing process excursions. A test cost for each corrective test is determined, and a total test cost for each of an incremental number of corrective tests is calculated. An effect of each corrective test on a reduction in the process excursions is determined, as is also the lost revenue for each process excursion. A reduction in the lost revenue for each of the incremental number of corrective tests is calculated, based at least in part on the effect of each corrective test on the reduction in process excursions and the revenue lost for each process excursion. An overall cost for each of the incremental number of corrective tests is calculated, based at least in part on a sum of the total test cost and the reduction in the lost revenue for each of the incremental number of corrective tests.

Abstract: A substrate that is adapted for the fabrication of integrated circuits, having an improved scribe mark. The scribe mark is small enough to fit within an edge exclusion zone of the substrate, is disposed wholly within the edge exclusion zone of the substrate, is not disposed on a backside of the substrate, and is readable by optical character recognition equipment. By placing the scribe mark within the edge exclusion zone of the substrate, in this manner, none of the space for salable dice is taken by the scribe mark. Further, the small size of the scribe mark reduces effects from chemical streaming, chemical mechanical polishing, and particulate expulsion. In addition, standard optical character recognition equipment can be used to read the scribe mark, without rendering the equipment unable to read prior art scribe marks.

Abstract: Incorporation of a sensor, such as an optical or laser based sensor, into a wafer edge processing unit, such as a WEE unit or mechanism. This sensor enables the WEE unit to be referenced to the wafer edge. Specifically, the sensor can be used to place a WEE unit in a fixed but accurate location at the beginning of the wafer edge expose process. Another approach is to have the WEE drive controller actively follow the edge of the wafer as it rotates during the WEE process, which has the advantage of compensating for any wafer centering errors as well as diameter and placement errors. In yet another approach, the edge sensor is used to sense and track the edge of a previous layer WEE pattern. The sensor can also facilitate the measuring of a distance from a wafer edge to a WEE edge feature.

Abstract: A method for determining component patterns of a raw substrate map. A subset of substrate patterns is selected from a set of substrate patterns, and combined into a composite substrate map. The substrate patterns are weighted. The composite substrate map is compared to the raw substrate map, and a degree of correlation between the composite substrate map and the raw substrate map is determined. The steps are iteratively repeated until the degree of correlation is at least a desired degree, and the weighted subset of substrate patterns is output as the component patterns of the raw substrate map.

Abstract: A method of determining the distance from an edge feature to a wafer edge. The wafer is put onto an image acquisition tool, and images are captured and classified. Based on the coordinates of the images and their classifications, the distance between an edge feature and the wafer edge is determined. Reference marks can be etched into the wafer to facilitate the measurement. The measurement technique is objective, and can be used to minimize the edge exclusion ring as well as defects that originate from the edge of the wafer.