Patents by Inventor Bruce Woolery

Bruce Woolery has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090323235
    Abstract: In some embodiments, semiconductor fabrication process charging protection is provided by coupling a first diode protection device to a high voltage node and coupling a second diode protection device to the first diode protection device at a second node. Other embodiments are described and claimed.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventors: Sangwoo Pae, Jeff Jones, Greg Taylor, Paul Packan, Bruce Woolery, Jeff Hicks
  • Patent number: 6531745
    Abstract: An n-well resistor device and its method of fabrication. The n-well resistor device of the present invention comprises a first n-type region and a second n-type region formed in an n-type silicon region. A gate dielectric layer formed on said n-type silicon region. A polysilicon gate formed on said gate dielectric.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: March 11, 2003
    Assignee: Intel Corporation
    Inventors: Bruce Woolery, Alper Ilkbahar
  • Patent number: 6528380
    Abstract: An n-well resistor device and its method of fabrication. The n-well resistor device of the present invention comprises a first n-type region and a second n-type region formed in an n-type silicon region. A gate dielectric layer formed on said n-type silicon region. A polysilicon gate formed on said gate dielectric.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: March 4, 2003
    Assignee: Intel Corporation
    Inventors: Bruce Woolery, Alper Ilkbahar
  • Publication number: 20010038128
    Abstract: An n-well resistor device and its method of fabrication. The n-well resistor device of the present invention comprises a first n-type region and a second n-type region formed in an n-type silicon region. A gate dielectric layer formed on said n-type silicon region. A polysilicon gate formed on said gate dielectric.
    Type: Application
    Filed: June 29, 2001
    Publication date: November 8, 2001
    Inventors: Bruce Woolery, Alper Ilkbahar