Abstract: Various embodiments provide a vertical-conduction semiconductor device that includes: a silicon substrate having a front face and a rear face; a front-side structure arranged on the front face of the substrate, having at least one current-conduction region at the front face; and a back side metal structure, arranged on the rear face of the substrate, in electrical contact with the substrate and constituted by a stack of metal layers. The back side metal structure is formed by: a first metal layer; a silicide region, interposed between the rear face of the substrate and the first metal layer and in electrical contact with the aforesaid rear face; and a second metal layer arranged on the first metal layer.

Abstract: A Chemical Mechanical Polishing, CMP, process applied to a wafer of Silicon Carbide having a thickness of, or lower than, 200 ?m, comprising the steps of: arranging the wafer on a supporting head of a CMP processing apparatus, the wafer having a front side and a back side opposite to one another, the front side housing at least one electronic component and being coupled to the supporting head; deliver a polishing slurry on the wafer, wherein the polishing slurry has a pH in the range 2-3; pressing the back side of the wafer against a polishing pad of the CMP apparatus exerting, by the supporting head, a pressure on the polishing pad in the range 5-20 kPa; setting a rotation of the polishing pad in the range 30-180 rpm, and setting a rotation of polishing head in the range 30-180 rpm; setting and maintaining a CMP process temperature equal to, or below, 50° C.

Abstract: Various embodiments provide a vertical-conduction semiconductor device that includes: a silicon substrate having a front face and a rear face; a front-side structure arranged on the front face of the substrate, having at least one current-conduction region at the front face; and a back side metal structure, arranged on the rear face of the substrate, in electrical contact with the substrate and constituted by a stack of metal layers. The back side metal structure is formed by: a first metal layer; a silicide region, interposed between the rear face of the substrate and the first metal layer and in electrical contact with the aforesaid rear face; and a second metal layer arranged on the first metal layer.