Abstract: A device and a method for aligning in time two essentially isochronous digital signals are provided, in which a plurality (2.sup.n) of replicas (CK1-CK4) of the first signal (CKIN), separated by a given phase difference, are generated and a number of said replicas (CK3, CK4) is subjected to sampling (4, 5) in correspondence with the rising edges of the second signal (DATA). As the result of the sampling, a combination of logic signals (SL0, SL1) is obtained which is representative of the phase relation existing between each of said replicas (CK1-CK4) and the second signal (DATA). The output signal (CKOUT) of the device, aligned with the second signal, corresponds to the one, among the replicas (CK1-CK4) of the first signal, which best reproduces the desired alignment condition.

Abstract: A circuit source has bias and modulation current generators for both p-type and n-type optical sources, and a pair of sources of control voltages for the bias and modulation current generators, which obtain pairs of control voltages from an adjustable driving current. An external signal allows selecting, by means of a control logic and CMOS gates, the generators required by the source. The circuit is made by using three pads of an integrated circuit, one for each control voltage source and the third comprising the current generators, the CMOS gates and the control logic.

Abstract: Transmitter module for optical interconnections, comprising a metal container housing an optical emitting device, an integrated circuit containing the driving circuit of the emitting device and an optical fibre extending outside the container, the emitting device being mounted on a metallic ground area realized on the integrated circuit. The cathode is electrically connected to the ground area and the anode is connected to a second metal area, connected with the output of the driving circuit. The module uses a type of assembly which minimises problems due to the length of the connecting wires, to parasitic effects and to the effects of signal reflections due to impedance mismatching. It also requires reduced power for its operation and it is provided with a structure facilitating dissipation.

Abstract: The device for the phase realignment of ATM cells in an optical ATM switching node is associated with each input line (Fe) of node and includes a circuit for recognizing the beginning of a cell, a circuit for evaluating the time shift between of a cell and a reference instant and for generating an error signal (ER) depending on the amount of time difference, and a delay line for compensating the time difference, driven by the error signal (ER). The time difference compensator means includes a logarithmic optical delay line that is connected upstream of the device for recognizing the beginning of a cell and for evaluating the amount of the time difference.

Abstract: The optical switch for fast cell-switching networks comprises an optical interconnection network (CM) and an electrical control network (CT). In order to fully exploit optical component capabilities and to overcome the constraints imposed by operating speed limits of electronic components, each input (IN1 . . . INk) of the interconnection network (CM) is associated with units (PAC1 . . . PACk) forming aggregates of cells which are to follow a same path through the interconnection network and time-compressing the aggregates, and each output (OU1 . . . OUk) is associated with units (PAD1 . . . PADk) for the time expansion of the aggregates and separation of the aggregate cells.

Abstract: A basic element for the interconnection network of a fast packet switching node, where a synchronization is made at bit input stream level, the cell beginning is identified and a stream conversion from the serial form to a word parallel form is performed. Cells are thus transformed in a completely parallel form and in the same form they are cyclically discharged in the subsequent cell time in a memory, where cells are written and read in a shared way on the basis of instructions given by a control unit, thus performing the switching function. The control unit is essentially based on the use of a content-addressed associative memory, where a fraction of the routing header and a code indicating the time sequence on which the cells are stored. Memory outgoing cells are reconverted from a completely parallel form to a form having the length of one word and therefore in a completely serial form at a bitrate equal to the input one.

Abstract: A switching unit for the selective transfer of bytes concurrently arriving in successive time slots over eight incoming signal paths to as many outgoing signal paths with intervening temporal and/or spatial transposition comprises a byte memory, loaded by way of a series/parallel converter and read out by way of a parallel/series converter, under the control of a routing memory dialoguing via a logic network with a microprocessor. The latter, through instructions sent to the logic network, may command the blocking of the readout from the byte memory onto an outgoing path during a given time slot, the insertion of a particular byte into such a time slot, or the transfer of selected bytes from either memory to the microprocessor itself. In particular, bytes from the first time slots of PCM frames arriving over selected signal paths can be so extracted from diagnostic purposes.

Abstract: An automatic exchange of a telephone system comprises a PCM switching network with a plurality of cascaded stages for establishing temporal and spatial connections between incoming channels on input lines of the first stage and outgoing channels on output lines of the last stage in response to commands from external controllers dialoguing with internal controllers of the network. Pairs of switching matrices forming part of nonadjacent stages are combined ito modular switching units each provided with its own internal controller. Routing instructions are transmitted from an external controller to a first internal controller which selects a signal path through the matrices of its own switching unit and informs a second internal controller of that selection whereupon the latter extends the path through an adjoining switching unit, and so on until the connection is completed.

Abstract: A switching unit for the selective transfer of bytes concurrently arriving in successive time slots over eight incoming signal paths to as many outgoing signal paths with intervening temporal and/or spatial transposition comprises a byte memory loaded by way of a series/parallel converter and read out by way of a parallel/series converter; two 8.times.8 storage matrices may alternately serve as the two converters. A routing memory, connected via a logic network to a command unit such as a microprocessor, controls the transfer and may also block the readout from the byte memory under certain conditions, specifically during an initiation procedure or where the switching unit is one of several such units forming part of a larger switching or concentration structure. In response to particular instructions from the command unit, a single byte from an incoming path may be transferred to one or all of the outgoing paths.