Patents by Inventor Bruno Conterno

Bruno Conterno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multilevel hierarchical multiprocessor computer system
    Patent number: 5586258
    Abstract: A multilevel multiprocessor system comprising a number of processing units, each comprising a number of multiprocessor modules connected to a first direct-access line to form a first hierarchical level (region); the processing units comprising subsets of multiprocessor modules connected to respective second direct-access lines to form a second hierarchical level (family); and each multiprocessor module comprising a number of processing modules connected to a direct-access (group) line connected to the first and second lines.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: December 17, 1996
    Assignee: Finmeccanica S.p.A.
    Inventors: Bruno Conterno, Mauro Gismondi, Vildo Luperini, Fernando Pesce
  • High-capacity memory having extended addressing capacity in a multiprocessing system
    Patent number: 5060186
    Abstract: A memory accessible by more than one external processor has a data capacity exceeding the addressing capacity of the processors and is capable of modifying the addressing data of the processors.
    Type: Grant
    Filed: September 11, 1989
    Date of Patent: October 22, 1991
    Assignee: Elettronica San Giorgio-Elsag S.p.A.
    Inventors: Giuseppe Barbagelata, Bruno Conterno, Fernando Pesce
  • Multiple-hierarchical-level multiprocessor system
    Patent number: 4814970
    Abstract: A multiple-hierarchical-level multiprocessor system having first numbers of processing modules comprising, each, at least one processor and connected to a first group of common direct-access communication lines for forming a first hierarchical level (family); a first processing module of each of the aforementioned first numbers also being connected to a second group of common direct-access communication lines for forming a second hierarchical level (region); a second number of the aforementioned second groups of common communication lines being interconnected via data transmitting and receiving means for forming a third hierarcical level (region network); the aforementioned means comprising at least one processor for enabling operation independent of the aforementioned modules.
    Type: Grant
    Filed: December 8, 1986
    Date of Patent: March 21, 1989
    Assignee: Elettronica San Giorgio - Elsag S.p.A.
    Inventors: Giuseppe Barbagelata, Bruno Conterno, Vildo Luperini, Enrico Perroni, Fernando Pesce, Osvaldo Pugliese