Abstract: Zener diodes of selectively variable breakdown voltages ranging from a few voltages to several hundred volts are fabricated in monolithic integrated circuits by locating the edge of a P-N junction at the surface of a substrate within the gradient region of P-type diffusion. Methods for making the same are also described.

Abstract: A triple diffused interdigitated NPN transistor formed in an isolated N-epitaxial pocket of an otherwise standard NPN bipolar junction isolated integrated circuit. The N-type diffused collector pocket in the N-epitaxial layer lowers collector resistance of the triple diffused NPN device.

Abstract: An MOS bucket brigade delay line having reduced parasitic capacitances include a first set of diffused drain source regions in a semiconductor substrate, a thin gate oxide layer overlying said diffused regions, a plurality of gate electrodes having first and second edges, the first edge of each electrode substantially overlapping one of said diffused regions, each of these elements formed in conventional manner. A second set of diffused drain-source regions extends the first set of regions by an amount limited by the second edge of the gate electrodes. The second set of drain source regions is formed by utilizing the gate electrodes as a diffusion mask.

Abstract: An MOS bucket brigade delay line having reduced parasitic capacitances and method for making the same, include a first set of diffused drain source regions in a semiconductor substrate, a thin gate oxide layer overlying said diffused regions, a plurality of gate electrodes having first and second edges, the first edge of each electrode substantially overlapping one of said diffused regions, each of these elements formed in conventional manner. A second set of diffused drain-source regions extends the first set of regions by an amount limited by the second edge of the gate electrodes. The second set of drain source regions is formed by utilizing the gate electrodes as a diffusion mask.

Abstract: A homogeneous integrated power structure embodies solid state control or signal devices and power devices integrated monolithically to achieve optimum physical characteristics of each device embodied therein at economical cost of manufacturing the same. The devices are electrically isolated from each other by a P-N junction isolation grid produced by the thermomigration of metal-rich wires through a semiconductor substrate by thermal gradient zone melting processing techniques.