Abstract: A light-emitting diode manufacturing method including the forming of three-dimensional semiconductor elements, extending along parallel axes, made of a III-V compound, each having a lower portion and a flared upper portion inscribed within a frustum of half apical angle ?. The method further comprises, for each semiconductor element, the forming of an active area covering the top of the upper portion and the forming of at least one semiconductor layer of the III-V compound covering the active area by vapor deposition at a pressure lower than 10 mPa, by using a flux of the group-III element along a direction inclined by an angle ?III and a flux of the group-V element along a direction inclined by an angle ?V with respect to the vertical axis, angles ?III and ?V being smaller than angle ?.

Abstract: A method of manufacturing an optoelectronic device including-light-emitting diodes comprising the forming of three-dimensional semiconductor elements made of a III-V compound, each comprising a lower portion and an upper portion and, for each semiconductor element, the forming of an active area covering the top of the upper portion and the forming of at least one semiconductor area of the III-V compound covering the active area. The upper portions are formed by vapor deposition at a pressure lower than 1.33 mPa.

Abstract: An optoelectronic device including one or a plurality of light-emitting diodes, each light-emitting diode including a three-dimensional semiconductor element, an active area resting on the three-dimensional semiconductor element and a stack of semiconductor layers covering the active area, the active area including a plurality of quantum wells, said stack being in mechanical contact with a plurality of quantum wells.

Abstract: A method of manufacturing an optoelectronic device including light-emitting diodes comprising forming three-dimensional semiconductor elements, extending along parallel axes, made of a III-V compound, with a polarity of the group-III element, the method further including, for each semiconductor element, forming an active area covering the semiconductor element and a stack of semiconductor layers covering the active area, the active area being formed by vapor deposition at low pressure and comprising quantum wells separated by barrier layers, each quantum well including a ternary alloy having at least one first group-III element, the group-V element, and a second group-III element, the ratio of the atomic flux of the group-III elements to the atomic flux of the group-V element is in the range from 1 to 1.8.

Abstract: The invention relates to a method for manufacturing a layer of interest (3) in a III-N crystalline compound by epitaxy from a layer of graphene (2), characterized in that it comprises, prior to a phase of nucleation of the layer of interest (3), a step of thermal treatment of the layer of graphene (2) in which it is subjected to a first temperature (Ttt) no lower than 1050° C. and to a stream of ammonia.

Abstract: The invention relates to a method for manufacturing a layer of interest (3) in a III-N crystalline compound by epitaxy from a layer of graphene (2), characterized in that it comprises, prior to a phase of nucleation of the layer of interest (3), a step of thermal treatment of the layer of graphene (2) in which it is subjected to a first temperature (Ttt) no lower than 1050° C. and to a stream of ammonia.

Abstract: The invention relates to an optoelectronic device (1) comprising at least one three-dimensional semiconductor structure (2) extending along a longitudinal axis (?) substantially orthogonal to a plane of a substrate (3) on which same lies, and comprising: a first doped portion (10), extending from one surface of the substrate (3) along the longitudinal axis (?); an active portion (30) comprising a passivation layer (34) and at least one quantum well (32) covered laterally by said passivation layer (34), the quantum well (32) of the active portion (30) having a mean diameter greater than that of said first doped portion (10), said active portion (30) extending from the first doped portion (10) along the longitudinal axis (?); and a second doped portion (20), extending from the active portion (30) along the longitudinal axis (?).

Abstract: The invention relates to an optoelectronic device (1) comprising at least one three-dimensional semiconductor structure (2) extending along a longitudinal axis (?) substantially orthogonal to a plane of a substrate (3) on which same lies, and comprising: a first doped portion (10), extending from one surface of the substrate (3) along the longitudinal axis (?); an active portion (30) comprising a passivation layer (34) and at least one quantum well (32) covered laterally by said passivation layer (34), the quantum well (32) of the active portion (30) having a mean diameter greater than that of said first doped portion (10), said active portion (30) extending from the first doped portion (10) along the longitudinal axis (?); and a second doped portion (20), extending from the active portion (30) along the longitudinal axis (?).

Abstract: A method for manufacturing at least one semiconductor structure, and a component including a structure formed with the method, the method including: providing a substrate including at least one semiconductor silicon surface; forming an amorphous silicon carbide layer in contact with at least one part of the semiconductor silicon surface; forming the at least one semiconductor structure in contact with the silicon carbide layer, the structure including at least one part, as a contact part, in contact with the surface of the silicon carbide layer, which includes gallium.

Abstract: A method for manufacturing at least one semiconductor structure, and a component including a structure formed with the method, the method including: providing a substrate including at least one semiconductor silicon surface; forming an amorphous silicon carbide layer in contact with at least one part of the semiconductor silicon surface; forming the at least one semiconductor structure in contact with the silicon carbide layer, the structure including at least one part, as a contact part, in contact with the surface of the silicon carbide layer, which includes gallium.