Abstract: The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. The memory stores a most significant address allocated to the memory within an extended memory array wherein the memory is incorporated or intended to be incorporated. A master memory signal is generated based on the most significant address allocated to the memory. A central processing unit executes a command for reading the register and supplies the content of the register to the serial input/output of the memory only if the memory is the master memory within the extended memory array. The memory includes slave memories whose operation depends upon the read/write status of the master memory.

Abstract: The present invention relates to a memory on a silicon microchip, comprising a serial input/output and an integrated memory array addressable under N bits. According to the present invention, the memory comprises means for storing a most significant address allocated to the memory within an extended memory array addressable with an extended address of N+K bits, an extended address counter for storing an extended address received at the serial input/output of the memory, the extended address comprising N least significant bits that are applied to the integrated memory array, and K most significant bits, means for comparing the K most significant bits with the most significant address allocated to the memory, and means for preventing the execution of a command for reading or writing the integrated memory array if the K most significant address bits are different to the most significant address allocated to the memory.

Abstract: The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. The memory stores a most significant address allocated to the memory within an extended memory array wherein the memory is incorporated or intended to be incorporated. A master memory signal is generated based on the most significant address allocated to the memory. A central processing unit executes a command for reading the register and supplies the content of the register to the serial input/output of the memory only if the memory is the master memory within the extended memory array. The memory includes slave memories whose operation depends upon the read/write status of the master memory.

Abstract: The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. The memory stores a most significant address allocated to the memory within an extended memory array wherein the memory is incorporated or intended to be incorporated. A master memory signal is generated based on the most significant address allocated to the memory. A central processing unit executes a command for reading the register and supplies the content of the register to the serial input/output of the memory only if the memory is the master memory within the extended memory array. The memory includes slave memories whose operation depends upon the read/write status of the master memory.

Abstract: The present invention relates to a memory in integrated circuit comprising a central Flash-type memory comprising memory cells forming pages, a buffer memory capable of storing binary words, and a sequencer for executing an instruction for saving, in a target page of the Flash memory, a series of external words received at an input terminal of the memory. According to the present invention, the sequencer is arranged for, after saving the series of external words in the buffer memory, saving, in the buffer memory, internal words present in the target page and corresponding, due to their address in the page, to locations of words in the buffer memory that have not received any external words, then erasing the target page and saving in the erased page the words present in the buffer memory.

Abstract: The present invention relates to a method for checking and refreshing a floating-gate transistor in the erased state, comprising the steps of applying a positive erase voltage to a control gate of the floating-gate transistor, and selectively applying a positive erase voltage to the drain of the floating-gate transistor, by means of a programming latch for example. Application to checking and refreshing memory pages in a Flash memory.

Abstract: An address decoder selectively applies to word lines of a memory array individual signals of variable polarity, negative or positive, the value of which varies according to a word line address applied to the decoder. The decoder comprises a group decoder delivering signals for selecting a group of word lines of variable polarity, at least one subgroup decoder delivering signals for selecting a subgroup of word lines of variable polarity, and word line drivers each comprising means for multiplexing the group and subgroup selection signals, for selecting and selectively applying one of these signals to a word line. Advantages: reduction in the size of the terminating elements of the decoders in relation with the reduction of the technological pitch in Flash memories.

Abstract: The present invention relates to a memory on a silicon microchip, comprising a serial input/output and an integrated memory array addressable under N bits. According to the present invention, the memory comprises means for storing a most significant address allocated to the memory within an extended memory array addressable with an extended address of N+K bits, an extended address counter for storing an extended address received at the serial input/output of the memory, the extended address comprising N least significant bits that are applied to the integrated memory array, and K most significant bits, means for comparing the K most significant bits with the most significant address allocated to the memory, and means for preventing the execution of a command for reading or writing the integrated memory array if the K most significant address bits are different to the most significant address allocated to the memory.

Abstract: The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. The memory stores a most significant address allocated to the memory within an extended memory array wherein the memory is incorporated or intended to be incorporated. A master memory signal is generated based on the most significant address allocated to the memory. A central processing unit executes a command for reading the register and supplies the content of the register to the serial input/output of the memory only if the memory is the master memory within the extended memory array. The memory includes slave memories whose operation depends upon the read/write status of the master memory.

Abstract: The present invention relates to a method for controlling and for refreshing memory cells in an electrically erasable and programmable memory comprising a memory array organized in sectors, each sector comprising memory cells linked to bit lines and to word lines. The method comprises controlling and refreshing memory cells of pages of the memory array the address of which is indicated by a control and refresh counter comprising data forming tokens usable once. According to the present invention, a control and refresh counter is integrated into each sector of the memory and comprises memory cells linked to the bit lines of the sector. A counter of a sector is erased after reaching a maximum counting value that is chosen so that, when this maximum counting value is reached, memory cells of the counter have undergone a number of electrical stress cycles that is at the most equal to a determined number. Application to Flash memories.

Abstract: An electrically erasable and programmable memory includes memory cells and a verify-program device. The memory also includes an erase verify device arranged for supplying an erase verify signal having a determined value when a datum read in a memory cell during a first verify-program cycle has an erase logic value. Application particularly to performing a blank verify test in serial input/output Flash memories.

Abstract: The present invention relates to a memory in integrated circuit comprising a central Flash-type memory comprising memory cells forming pages, a buffer memory capable of storing binary words, and a sequencer for executing an instruction for saving, in a target page of the Flash memory, a series of external words received at an input terminal of the memory. According to the present invention, the sequencer is arranged for, after saving the series of external words in the buffer memory, saving, in the buffer memory, internal words present in the target page and corresponding, due to their address in the page, to locations of words in the buffer memory that have not received any external words, then erasing the target page and saving in the erased page the words present in the buffer memory.

Abstract: The present invention relates to a method for checking and refreshing a floating-gate transistor in the erased state, comprising the steps of applying a positive erase voltage to a control gate of the floating-gate transistor, and selectively applying a positive erase voltage to the drain of the floating-gate transistor, by means of a programming latch for example. Application to checking and refreshing memory pages in a Flash memory.

Abstract: An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel. The integrated circuit memory may include a buffer memory with a sufficient capacity to store a plurality of words, the output of which is coupled to the input of the FLASH memory. A circuit is also included for recording into the buffer memory a series of words to be recorded into the FLASH memory and recording into the FLASH memory the words first recorded into the buffer memory.

Abstract: An electrically erasable and programmable memory includes memory cells and a verify-program device. The memory also comprises an erase verify device arranged for supplying an erase verify signal having a determined value when a datum read in a memory cell during a first verify-program cycle has an erase logic value. Application particularly to performing a blank verify test in serial input/output Flash memories.

Abstract: An address decoder selectively applies to word lines of a memory array individual signals of variable polarity, negative or positive, the value of which varies according to a word line address applied to the decoder. The decoder comprises a group decoder delivering signals for selecting a group of word lines of variable polarity, at least one subgroup decoder delivering signals for selecting a subgroup of word lines of variable polarity, and word line drivers each comprising means for multiplexing the group and subgroup selection signals, for selecting and selectively applying one of these signals to a word line. Advantages: reduction in the size of the terminating elements of the decoders in relation with the reduction of the technological pitch in Flash memories.

Abstract: The present invention relates to a method for controlling and for refreshing memory cells in an electrically erasable and programmable memory comprising a memory array organized in sectors, each sector comprising memory cells linked to bit lines and to word lines. The method comprises controlling and refreshing memory cells of pages of the memory array the address of which is indicated by a control and refresh counter comprising data forming tokens usable once. According to the present invention, a control and refresh counter is integrated into each sector of the memory and comprises memory cells linked to the bit lines of the sector. A counter of a sector is erased after reaching a maximum counting value that is chosen so that, when this maximum counting value is reached, memory cells of the counter have undergone a number of electrical stress cycles that is at the most equal to a determined number. Application to Flash memories.

Abstract: The present invention relates to a page-erasable FLASH memory including a memory array having a plurality of pages each with floating-gate transistors connected by their gates to word lines, a word line decoder connected to the word lines of the memory, and the application of a positive erase voltage to the source or drain electrodes of all the floating-gate transistors of a sector forming a page to be erased. According to the present invention, the word line decoder includes a unit for applying, when a page is being erased, a negative erase voltage to the gates of the transistors of the page to be erased, while applying a positive inhibit voltage to the gates of the transistors of at least one page that is not to be erased.

Abstract: A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.

Abstract: The present invention relates to a page-erasable FLASH memory including a memory array having a plurality of pages each with floating-gate transistors connected by their gates to word lines, a word line decoder connected to the word lines of the memory, and the application of a positive erase voltage to the source or drain electrodes of all the floating-gate transistors of a sector forming a page to be erased. According to the present invention, the word line decoder includes a unit for applying, when a page is being erased, a negative erase voltage to the gates of the transistors of the page to be erased, while applying a positive inhibit voltage to the gates of the transistors of at least one page that is not to be erased.