Patents by Inventor Bruno Sallé

Bruno Sallé has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250141390
    Abstract: Disclosed herein are devices, systems, and methods for a motor control unit adapted to control an electrical motor. The motor control unit includes a digital control unit having one or more output ports and a safety component provided to at least one of the output ports. The safety component provides a predetermined safe value upon receipt of a fault signal derived from measurement signals otherwise provides to the electrical motor an output from the digital control unit. The safety component includes a switching means connected to the output ports and to a storage unit that stores the predetermined safe value. The switching means is controlled by the fault signal and the storage unit is adapted for receiving the predetermined safe value either directly or indirectly.
    Type: Application
    Filed: November 11, 2024
    Publication date: May 1, 2025
    Inventors: Mathieu THOMAS, Khaled DOUZANE, Bruno SALLE
  • Publication number: 20240022202
    Abstract: The invention relates to the application domain of vehicle electric motor digital control and more specifically to the domain of functional safety mechanisms associated to that.
    Type: Application
    Filed: November 27, 2020
    Publication date: January 18, 2024
    Inventors: Bruno SALLE, Anselme LEBRUN
  • Patent number: 9274909
    Abstract: An apparatus and method for error management in an integrated circuit system are presented. An error management unit (EMU) apparatus manages critical and non-critical errors that may be masked or non-masked. An EMU includes an EMU state machine, having a BOOT state, a CONFIG state, a FUNCT state, a WARNING state and an ERROR state. The method discloses transitions in the EMU state machine. While in the ERROR state an error reaction may be applied. The objective of the error reaction is to recover errors by software and hardware means. The EMU may further appropriately alert the system while in ERROR state and therefore be used as a safety mechanism permitting to collect error signals issued by fault detector units and can further cause action on faulty units for recovery purposes.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: March 1, 2016
    Assignee: Scaleo Chip
    Inventor: Bruno Sallé
  • Publication number: 20150058669
    Abstract: An apparatus and method for error management in an integrated circuit system are presented. An error management unit (EMU) apparatus manages critical and non-critical errors that may be masked or non-masked. An EMU includes an EMU state machine, having a BOOT state, a CONFIG state, a FUNCT state, a WARNING state and an ERROR state. The method discloses transitions in the EMU state machine. While in the ERROR state an error reaction may be applied. The objective of the error reaction is to recover errors by software and hardware means. The EMU may further appropriately alert the system while in ERROR state and therefore be used as a safety mechanism permitting to collect error signals issued by fault detector units and can further cause action on faulty units for recovery purposes.
    Type: Application
    Filed: November 19, 2013
    Publication date: February 26, 2015
    Applicant: SCALEO CHIP
    Inventor: Bruno Sallé