Abstract: An apparatus and method for error management in an integrated circuit system are presented. An error management unit (EMU) apparatus manages critical and non-critical errors that may be masked or non-masked. An EMU includes an EMU state machine, having a BOOT state, a CONFIG state, a FUNCT state, a WARNING state and an ERROR state. The method discloses transitions in the EMU state machine. While in the ERROR state an error reaction may be applied. The objective of the error reaction is to recover errors by software and hardware means. The EMU may further appropriately alert the system while in ERROR state and therefore be used as a safety mechanism permitting to collect error signals issued by fault detector units and can further cause action on faulty units for recovery purposes.

Abstract: An apparatus and method for error management in an integrated circuit system are presented. An error management unit (EMU) apparatus manages critical and non-critical errors that may be masked or non-masked. An EMU includes an EMU state machine, having a BOOT state, a CONFIG state, a FUNCT state, a WARNING state and an ERROR state. The method discloses transitions in the EMU state machine. While in the ERROR state an error reaction may be applied. The objective of the error reaction is to recover errors by software and hardware means. The EMU may further appropriately alert the system while in ERROR state and therefore be used as a safety mechanism permitting to collect error signals issued by fault detector units and can further cause action on faulty units for recovery purposes.