Patents by Inventor Bruno Spuler
Bruno Spuler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6984556Abstract: A two-step etch process is used to form a vertical collar oxide within the upper portion of a trench capacitor. The first step uses CF4/SiF4/O2 chemistry and ends when the bottom of the collar within the trench is opened although a thin oxide layer still remains on the surface of the PAD-nitride. The second etch step uses C4F8 chemistry to completely remove the remaining silicon oxide layer. The process provides a good uniformity in thickness of the PAD-nitride layer and sufficient collar oxide thickness in the very top section of the collar oxide. The process is applicable for manufacturing deep trench capacitors for DRAM devices.Type: GrantFiled: June 24, 2002Date of Patent: January 10, 2006Assignee: Infineon Technologies AGInventors: Christian Drabe, Jana Haensel, Anke Krasemann, Barbara Lorenz, Thomas Morgenstern, Torsten Schneider, Bruno Spuler
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Publication number: 20040198015Abstract: A two-step etch process is used to form a vertical collar oxide within the upper portion of a trench capacitor. The first step uses CF4/SiF4/O2 chemistry and ends when the bottom of the collar within the trench is opened although a thin oxide layer still remains on the surface of the PAD-nitride. The second etch step uses C4F8 chemistry to completely remove the remaining silicon oxide layer. The process provides a good uniformity in thickness of the PAD-nitride layer and sufficient collar oxide thickness in the very top section of the collar oxide. The process is applicable for manufacturing deep trench capacitors for DRAM devices.Type: ApplicationFiled: May 14, 2004Publication date: October 7, 2004Inventors: Christian Drabe, Jana Haensel, Anke Krasemann, Barbara Lorenz, Thomas Morgenstern, Torsten Schneider, Bruno Spuler
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Patent number: 6784553Abstract: A semiconductor device and a method for manufacturing the semiconductor device with a self-aligned contact, is described. A first conductor and a second conductor are formed on the surface of the semiconductor substrate. The first conductor and the second conductor are encapsulated with a first encapsulation and a second encapsulation, respectively. The first encapsulation and the second encapsulation contain titanium oxide, boron nitride, silicon carbide, magnesium oxide or carbon. The first encapsulation and the second encapsulation are suitable as a self-aligning etch mask for etching a self-aligned contact hole between the first conductor and the second conductor.Type: GrantFiled: June 11, 2002Date of Patent: August 31, 2004Assignee: Infineon Technologies SC300 GmbH & Co. KGInventors: Ralf Zedlitz, Bruno Spuler
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Patent number: 6593254Abstract: There is disclosed a method for clamping a semiconductor wafer, preferably suitable for a wafer with a diameter of 300 mm or larger. After depositing at least one encapsulating material layer over the front side and backside of the wafer, the material layer over the front side of the wafer is etched selectively to form a predetermined structure in following process steps. Wafer warpage is caused as a result of unequal wafer bowing stress of the material layer. By removing the material layer over the backside of the wafer partially or completely in accordance with the desired reduction of the bowing stress wafer warpage is reduced. In a further course of the manufacturing process, the semiconductor device is clamped electrostatically, physically or by use of vacuum.Type: GrantFiled: March 28, 2002Date of Patent: July 15, 2003Assignee: Infineon Technologies AGInventors: Manfred Kraxenberger, Ines Thümmel, Bruno Spuler, Thorsten Schedel, Karl Mautz
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Patent number: 6521542Abstract: A method is provided for forming a step in a layer of material. The method includes forming the layer over a substrate. A cavity is formed in a portion of an upper surface of the layer. The formed cavity is filled with a filler material to provide a substantially planar surface over the substrate. A photoresist layer is formed over the substantially planar surface over the substrate. An aperture is formed in the photoresist layer in registration with the formed cavity. The aperture exposes a portion of the filler material. The exposed portion of the filler material is removed along with a contiguous portion of the layer to form the step in the indentation. The cavity may be either a trench or a via. A “Trench First” approach and a “Via First” approach are described.Type: GrantFiled: June 14, 2000Date of Patent: February 18, 2003Assignees: International Business Machines Corp., Infineon Technologies AGInventors: Mike Armacost, Bruno Spuler, Gabriela Brase, Alois Gutmann
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Publication number: 20020187630Abstract: A semiconductor device and a method for manufacturing the semiconductor device with a self-aligned contact, is described. A first conductor and a second conductor are formed on the surface of the semiconductor substrate. The first conductor and the second conductor are encapsulated with a first encapsulation and a second encapsulation, respectively. The first encapsulation and the second encapsulation contain titanium oxide, boron nitride, silicon carbide, magnesium oxide or carbon. The first encapsulation and the second encapsulation are suitable as a self-aligning etch mask for etching a self-aligned contact hole between the first conductor and the second conductor.Type: ApplicationFiled: June 11, 2002Publication date: December 12, 2002Inventors: Ralf Zedlitz, Bruno Spuler
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Publication number: 20020132393Abstract: There is disclosed a method for clamping a semiconductor wafer, preferably suitable for a wafer with a diameter of 300 mm or larger. After depositing at least one encapsulating material layer over the front side and backside of the wafer, the material layer over the front side of the wafer is etched selectively to form a predetermined structure in following process steps. Wafer warpage is caused as a result of unequal wafer bowing stress of the material layer. By removing the material layer over the backside of the wafer partially or completely in accordance with the desired reduction of the bowing stress wafer warpage is reduced. In a further course of the manufacturing process, the semiconductor device is clamped electrostatically, physically or by use of vacuum.Type: ApplicationFiled: March 28, 2002Publication date: September 19, 2002Inventors: Manfred Kraxenberger, Ines Thummel, Bruno Spuler, Thorsten Schedel, Karl Mautz
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Patent number: 6379869Abstract: A photoresist system is provided that is easily structurable and is suitable for deep ultraviolet range patterning. An increased etching resistance to oxygen-containing plasma is produced in a lithographically generated photoresist structure by treatment with an etch protectant. The etch protectant includes a silylating agent for chemical reaction with reactive groups of the photoresist. In an embodiment, the photoresist includes a base resin initially containing no aromatic groups. Silylating agents include silicon tetrachloride, silicon tetrafluoride, trichlorosilane, dimethylchlorosilane and hexamethyldisilazane.Type: GrantFiled: March 31, 1999Date of Patent: April 30, 2002Assignee: Infineon Technologies AGInventors: Uwe Paul Schroeder, Gerhard Kunkel, Alois Gutmann, Bruno Spuler
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Patent number: 6177353Abstract: A method for reducing polymer deposition on vertical surfaces of metal lines etched from a metallization layer disposed above a substrate. The method includes forming a hard mask layer above the metallization layer and providing a photoresist mask above the hard mask layer. The method further includes employing the photoresist mask to form a hard mask from the hard mask layer. The hard mask has patterns therein configured to form the metal lines in a subsequent plasma-enhanced metallization etch. There is also included removing the photoresist mask. Additionally, there is included performing the plasma-enhanced metallization etch employing the hard mask and an etchant source gas that includes Cl2 and at least one passivation-forming chemical, wherein the plasma-enhanced metallization etch is performed without employing photoresist to reduce the polymer deposition during the plasma-enhanced metallization etch.Type: GrantFiled: September 15, 1998Date of Patent: January 23, 2001Assignee: Infineon Technologies North America Corp.Inventors: Martin Gutsche, Peter Strobl, Stephan Wege, Eike Lueken, Georg Stojakovic, Bruno Spuler
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Patent number: 6071820Abstract: A method for forming integrated circuit conductors. The method includes the steps of placing in a reactive ion etching chamber a semiconductor body having disposed over a surface thereof: a metalization layer comprising an aluminum layer disposed between a pair of barrier metal layers; and, a photoresist layer disposed on a selected portion of a surface of an upper one of the pair of barrier layers. Radio frequency energy is inductively coupled into the chamber while silicon tetrachloride and chlorine are introduced into the chamber at rates selected to etch portions of the metalization layer exposed by the photoresist with aluminum having substantially vertical sidewalls. The silicon tetrachloride is introduced into the chamber at a rate in the range of 4 to 8 sccm. The rate of the chlorine is in the range of 50 sccm to 150 sccm. The chamber is at a pressure of about 12 milliTorr during the etching of the metalization layer.Type: GrantFiled: September 30, 1997Date of Patent: June 6, 2000Assignee: Siemens AktiengesellschaftInventors: Virinder Grewal, Bruno Spuler
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Patent number: 6033984Abstract: An improved method of forming a bond pad (222) by performing a dual damascene etch through a layer stack (200) disposed above a substrate (204) using self aligned vias (216). The layer (200) stack includes an underlying conductive layer (208) and an insulating layer (202) disposed above the underlying conductive layer (208). The method includes the following operative steps. At least a via hole (216) is formed in the insulating layer (202) positioned over the underlying device layer (208) and extending to the underlying device layer (208) at the bottom of the via hole. A bond pad trench (218) is then formed that takes the form of the desired bond pad (222). A layer of conductive material (220) is then placed over the insulating layer (202) substantially simultaneously filling the via hole (216) and the bond pad trench (218). The bond pad (222) is then formed by removing the layer of conductive material (220) sufficient to expose the upper surface of the insulating layer (210).Type: GrantFiled: December 23, 1997Date of Patent: March 7, 2000Assignee: Siemens AktiengesellschaftInventors: Rainer Florian Schnabel, Xian J. Ning, Bruno Spuler
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Patent number: 5976986Abstract: RIE of metallization is achieved at low power and low pressure using Cl.sub.2 and HCl as reactant species by creating a transformer coupled plasma with power applied to electrodes positioned both above and below a substrate with metallization thereon to be etched. Three layer metallizations which include bulk aluminum or aluminum alloy sandwiched between barrier layers made from, for example, Ti/TiN, are etched in a three step process wherein relatively lower quantities of Cl.sub.2 are used in the plasma during etching of the barrier layers and relatively higher quantities of Cl.sub.2 are used during etching of the bulk aluminum or aluminum alloy layer. The ratio of etchants Cl.sub.2 and HCl and an inert gas, such as N.sub.2 are controlled in a manner such that a very thin side wall layer (10-100 .ANG.) of reaction byproducts created during RIE are deposited on the side walls of trenches formed in the metallization during etching.Type: GrantFiled: August 6, 1996Date of Patent: November 2, 1999Assignees: International Business Machines Corp., Siemens Aktiengesellschaft, Kabushiki Kaisha ToshibaInventors: Munir D. Naeem, Stuart M. Burns, Rosemary Christie, Virinder Grewal, Walter W. Kocon, Masaki Narita, Bruno Spuler, Chi-Hua Yang
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Patent number: 5935873Abstract: A method for forming a Self Aligned Contact in a semiconductor device includes incorporating carbon into a nitride layer during or following the formation of the nitride layer on a semiconductor substrate.Type: GrantFiled: September 29, 1997Date of Patent: August 10, 1999Assignee: Siemens AktiengesellschaftInventors: Bruno Spuler, Juergen Wittmann, Martin Gutsche, Wolfgang Bergner, Matthias Ilg
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Patent number: 5874363Abstract: Metal silicide is removed at a faster rate than polysilicon in dry etching of metal silicide/polysilicon composites with an etching gas made from HCl and Cl.sub.2 at a volumetric flowrate ratio of HCl:Cl.sub.2 within the range of 3:1 to 5:1.Type: GrantFiled: May 13, 1996Date of Patent: February 23, 1999Assignees: Kabushiki Kaisha Toshiba, International Business Machines Corporation, Siemens Components, Inc.Inventors: Peter D. Hoh, Tokuhisa Ohiwa, Virinder Grewal, Bruno Spuler, Waldemar Kocon, Guadalupe Wiltshire
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Patent number: 5854126Abstract: A method for forming a plurality of electrically conductive wires on a substrate. The method includes forming a relatively non-planar metal layer over a surface of the substrate. A self-planarizing material is deposited over the metal layer. The self-planarizing material forms a planarization layer over the surface of the metal layer. The planarization layer has a surface relatively planar compared to the relatively non-planar metal layer. A photoresist layer is deposited over the surface of the planarization layer. The photoresist layer is patterned with a plurality of grooves to form a mask with such grooves exposing underling portions of the planarization layer. The photoresist mask is used as a mask to etch grooves in the exposed portions of the planarization layer and thereby form a second mask. The second mask exposes underling portions of the relatively non-planar metal layer.Type: GrantFiled: March 31, 1997Date of Patent: December 29, 1998Assignee: Siemens AktiengesellschaftInventors: Dirk Tobben, Bruno Spuler, Martin Gutsche, Peter Weigand
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Patent number: 5846884Abstract: A method in a plasma processing chamber for etching through a selected portion of a layer stack. The layer stack comprises a metallization layer, a first barrier layer disposed adjacent to the metallization layer, and a photoresist layer disposed above the metallization layer. The method includes etching at least partially through the first barrier layer using a high sputter component etch. The method further includes etching at least partially through the metallization layer using a low sputter component etch. The low sputter component etch has a sputter component lower than a sputter component of the high sputter component etch.Type: GrantFiled: June 20, 1997Date of Patent: December 8, 1998Assignees: Siemens Aktiengesellschaft, International Business Machines Corporation, Kabushiki Kaisha ToshibaInventors: Munir D. Naeem, Stuart M. Burns, Nancy Greco, Steve Greco, Virinder Grewal, Ernest Levine, Masaki Narita, Bruno Spuler