Patents by Inventor Bruno Vieira Da Cunha Martins

Bruno Vieira Da Cunha Martins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Treating a silicon on insulator wafer in preparation for manufacturing an atomistic electronic device interfaced with a CMOS electronic device
    Patent number: 11749558
    Abstract: A method for treating a wafer is provided with a portion of a semiconductor layer is selectively removed from the wafer so as to create an inactive region of the wafer surrounding a first active region of the wafer. The inactive region of the wafer has an exposed portion of an insulator layer, but none of the semiconductor layer. The first active region of the wafer includes a first portion of the semiconductor layer and a first portion of the insulator layer. At least one conductor is formed in contact with the first portion of the semiconductor layer, such that the conductor and the first portion of the semiconductor layer form a portion of an electrical circuit. The first active region of the wafer is selectively treated to remove a native oxide layer from the first portion of the semiconductor layer. A resulting wafer is also disclosed.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: September 5, 2023
    Assignees: Quantum Silicon Inc., The Governors of the University of Alberta, National Research Council of Canada
    Inventors: Bruno Vieira Da Cunha Martins, Robert A. Wolkow, Marco Taucer, Jason Pitters
  • TREATING A SILICON ON INSULATOR WAFER IN PREPARATION FOR MANUFACTURING AN ATOMISTIC ELECTRONIC DEVICE INTERFACED WITH A CMOS ELECTRONIC DEVICE
    Publication number: 20220102197
    Abstract: A method for treating a wafer is provided with a portion of a semiconductor layer is selectively removed from the wafer so as to create an inactive region of the wafer surrounding a first active region of the wafer. The inactive region of the wafer has an exposed portion of an insulator layer, but none of the semiconductor layer. The first active region of the wafer includes a first portion of the semiconductor layer and a first portion of the insulator layer. At least one conductor is formed in contact with the first portion of the semiconductor layer, such that the conductor and the first portion of the semiconductor layer form a portion of an electrical circuit. The first active region of the wafer is selectively treated to remove a native oxide layer from the first portion of the semiconductor layer. A resulting wafer is also disclosed.
    Type: Application
    Filed: December 13, 2021
    Publication date: March 31, 2022
    Applicants: Quantum Silicon Inc., The Governors of the University of Alberta, National Research Council of Canada
    Inventors: Bruno Vieira Da Cunha Martins, Robert A. Wolkow, Marco Taucer, Jason Pitters
  • Treating a silicon on insulator wafer in preparation for manufacturing an atomistic electronic device interfaced with a CMOS electronic device
    Patent number: 11232976
    Abstract: A method for treating a wafer is provided with a portion of a semiconductor layer is selectively removed from the wafer so as to create an inactive region of the wafer surrounding a first active region of the wafer. The inactive region of the wafer has an exposed portion of an insulator layer, but none of the semiconductor layer. The first active region of the wafer includes a first portion of the semiconductor layer and a first portion of the insulator layer. At least one conductor is formed in contact with the first portion of the semiconductor layer, such that the conductor and the first portion of the semiconductor layer form a portion of an electrical circuit. The first active region of the wafer is selectively treated to remove a native oxide layer from the first portion of the semiconductor layer. A resulting wafer is also disclosed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 25, 2022
    Assignees: National Research Council of Canada, The Governors of the University of Alberta, Quantum Silicon Inc.
    Inventors: Bruno Vieira Da Cunha Martins, Robert A. Wolkow, Marco Taucer, Jason Pitters
  • TREATING A SILICON ON INSULATOR WAFER IN PREPARATION FOR MANUFACTURING AN ATOMISTIC ELECTRONIC DEVICE INTERFACED WITH A CMOS ELECTRONIC DEVICE
    Publication number: 20210159116
    Abstract: A method for treating a wafer is provided with a portion of a semiconductor layer is selectively removed from the wafer so as to create an inactive region of the wafer surrounding a first active region of the wafer. The inactive region of the wafer has an exposed portion of an insulator layer, but none of the semiconductor layer. The first active region of the wafer includes a first portion of the semiconductor layer and a first portion of the insulator layer. At least one conductor is formed in contact with the first portion of the semiconductor layer, such that the conductor and the first portion of the semiconductor layer form a portion of an electrical circuit. The first active region of the wafer is selectively treated to remove a native oxide layer from the first portion of the semiconductor layer. A resulting wafer is also disclosed.
    Type: Application
    Filed: June 29, 2018
    Publication date: May 27, 2021
    Applicants: Quantum Silicon Inc., The Governors of the University of Alberta, National Research Council of Canada
    Inventors: Bruno Vieira Da Cunha Martins, Robert A. Wolkow, Marco Taucer, Jason Pitters