Abstract: An exercise apparatus includes a base having a rear end and a front end. A support extends upright from the front end of the base and supports a handle assembly disposed at an elevated location relative to the front end of the base. A framework, between the rear end of the base and the front end of the base, is mounted to the rear end of the base for movement of the framework between a lowered inclined position relative to the rear end of the base and a raised inclined position relative to the rear end of the base, and for side-to-side pivotal movement of the framework about a longitudinal axis. Opposed foot supports are mounted to the framework on either side of the longitudinal axis for movement in reciprocal directions relative to the handle assembly.

Abstract: An exercise apparatus includes a base having a rear end and a front end. A support extends upright from the front end of the base and supports a handle assembly disposed at an elevated location relative to the front end of the base. A framework, between the rear end of the base and the front end of the base, is mounted to the rear end of the base for movement of the framework between a lowered inclined position relative to the rear end of the base and a raised inclined position relative to the rear end of the base, and for side-to-side pivotal movement of the framework about a longitudinal axis. Opposed foot supports are mounted to the framework on either side of the longitudinal axis for movement in reciprocal directions relative to the handle assembly.

Abstract: A system for running in, in which multiple PCI bus connections are each bridged to multiple boards-under-test. The presence or absence of power in each of these bus connections is monitored, and the boards-under-test are correspondingly powered up (or not). Multiple test-bed subboards are preferably used, each with multiple sockets for receiving boards-under-test with high-insertion-force connectors, and the independent power control permits the boards-under-test on one subboard to be powered off and swapped while the boards-under-test on the other subboard are still being exercised. Preferable a single movable extractor mechanism is mounted on each subboard, and can be positioned (with respect to any one of the high-insertion-force connectors) for linear extraction of the board-under-test without any torque.

Abstract: An embodiment of the present invention provides a peripheral controller for coupling a mass storage peripheral to a computer system. In a disclosed embodiment the peripheral controller is a disk array controller programmed for RAID. The peripheral controller includes a first messaging unit (FMU), a second messaging unit (SMU), and a peripheral interface which are connected by a local bus. The FMU responds to messages from a first operating system driver. The SMU responds to messages from a different second operating system driver. In one embodiment, the FMU responds to commands from the first operating system driver which is non-standard. In another embodiment, the SMU responds to commands from the second operating system driver which is compatible with the I2O standard. In the disclosed embodiment, the peripheral interface controls mass storage peripherals in response to messages sent to the FMU or the SMU.

Abstract: An embodiment of the present invention discloses a technique for concealing a peripheral memory transaction on a local bus within a peripheral controller from a host system bus. In the preferred embodiment both the local bus and the host system bus are PCI buses. The technique is implemented when a peripheral memory transaction is detected on the local bus. In a disclosed embodiment, the peripheral memory transaction is detected by monitoring command and byte enables (CBEs) and five upper address bits (AD[31::27]) of the local bus. A peripheral memory transaction is indicated when a memory transaction on the local bus is directed to an upper 128 MB of 4 GB host memory. When a memory transaction is detected to the upper 128 MB of memory the transaction is intercepted. The interception is accomplished by blocking the CBEs on the local bus from a peripheral interface.The peripheral interface in the preferred embodiment is a standard PCI--PCI bridge which couples the local bus to the host system bus.

Abstract: An embodiment of the present invention discloses a technique that allows hot plugging a peripheral controller card, containing both a local bus and a peripheral bus on a single connector, into a host system board containing a host system bus and a host I/O bus. When mating the peripheral controller card to the host system board a local device power supply (LDPS) is inactive, a peripheral device power bus (PDPB) is powered, and signal lines of a peripheral device are maintained in a high impedance state. Following a delay after the mating, the LDPS is activated by the host operating system (OS). Following the activation of the LDPS, the host system bus is coupled to the single connector through switches that are under OS control. In response to the activation of the LDPS, the signal lines of the peripheral device are enabled.In a disclosed embodiment the peripheral controller card is a disk array controller card, the local bus is a PCI bus, and the peripheral bus is a SCSI bus.