Patents by Inventor Bryan Christian BACQUIAN

Bryan Christian BACQUIAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11404355
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: August 2, 2022
    Assignees: STMICROELECTRONICS PTE LTD, STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Bryan Christian Bacquian, Maiden Grace Maming, David Gani
  • Publication number: 20200365492
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Application
    Filed: July 31, 2020
    Publication date: November 19, 2020
    Inventors: Rennier RODRIGUEZ, Bryan Christian BACQUIAN, Maiden Grace MAMING, David GANI
  • Patent number: 10763194
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 1, 2020
    Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS PTE LTD
    Inventors: Rennier Rodriguez, Bryan Christian Bacquian, Maiden Grace Maming, David Gani
  • Publication number: 20190096788
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Application
    Filed: September 22, 2017
    Publication date: March 28, 2019
    Inventors: Rennier Rodriguez, Bryan Christian Bacquian, Maiden Grace Maming, David Gani
  • Publication number: 20170084490
    Abstract: A method is for making an integrated circuit (IC) device. The method may include dicing a wafer into IC dies, each IC die having an active surface, a back surface opposite the active surface, and a sidewall with a step defining a smaller periphery adjacent the back surface and a larger periphery adjacent the active surface. The method may include positioning a resin material between the back surface of each IC die and a respective substrate, and around each IC die so that the resin material abuts and is retained by the step.
    Type: Application
    Filed: September 18, 2015
    Publication date: March 23, 2017
    Inventors: Bryan Christian Bacquian, Frederick Arellano, Aiza Marie Agudon
  • Patent number: 9177903
    Abstract: A method of assembling a multi-chip electronic device into a thin electronic package entails inverting a flip-chip die arrangement over a hollow substrate, stacking additional dies on the hollow substrate to form a multi-chip electronic device, and encapsulating the multi-chip electronic device. Containment of the encapsulant can be achieved by joining split substrate portions, or by reinforcing a hollow unitary substrate, using a removable adhesive film. Use of the removable adhesive film facilitates surrounding the multi-chip electronic device with the encapsulant. The adhesive film can also prevent encapsulant from creeping around the substrate to an underside of the substrate that supports solder ball pads for subsequent attachment to a ball grid array (BGA) or a land grid array (LGA).
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: November 3, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Bernie Chrisanto Ang, Bryan Christian Bacquian
  • Publication number: 20140291842
    Abstract: A method of assembling a multi-chip electronic device into a thin electronic package entails inverting a flip-chip die arrangement over a hollow substrate, stacking additional dies on the hollow substrate to form a multi-chip electronic device, and encapsulating the multi-chip electronic device. Containment of the encapsulant can be achieved by joining split substrate portions, or by reinforcing a hollow unitary substrate, using a removable adhesive film. Use of the removable adhesive film facilitates surrounding the multi-chip electronic device with the encapsulant. The adhesive film can also prevent encapsulant from creeping around the substrate to an underside of the substrate that supports solder ball pads for subsequent attachment to a ball grid array (BGA) or a land grid array (LGA).
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Applicant: STMicroelectronics, Inc.
    Inventors: Bernie Chrisanto ANG, Bryan Christian BACQUIAN