Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth long distance communication, e.g. photonic or electronic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication.

Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit; a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and/or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween.

Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication.

Abstract: A system and method for controlling memory operations is disclosed. In a particular embodiment, the system includes a memory controller that can request control of a contact that is shared between a first memory device and a second memory device. In a particular embodiment, the memory controller includes a state machine to request and receive control of the contact. In another particular embodiment, the first memory device is a non-volatile memory device and the second memory device is a volatile memory device.

Abstract: A system and method for controlling memory operations is disclosed. In a particular embodiment, the system includes a memory controller that can request control of a contact that is shared between a first memory device and a second memory device. In a particular embodiment, the memory controller includes a state machine to request and receive control of the contact. In another particular embodiment, the first memory device is a non-volatile memory device and the second memory device is a volatile memory device.

Abstract: A device, system and method for controlling memory operations are disclosed. In an embodiment, data is received at one of multiple slave devices in an integrated circuit. The data is received from at least one bus in a multiple layer bus and is provided to a memory controller. The data is stored in a selected one of multiple memory banks. The memory banks are interleaved such that a first memory address resides on a first memory bank and a next memory address resides on a second memory bank.

Abstract: An attenuator includes a first stage 601a having a first operational amplifier 602a and a tapped resistor 603a. Tapped resistor 603a has an input for receiving input data, an output coupled to an output of first operational amplifier 602a, and a plurality of taps for selectively presenting a sequence of voltages to a noninverting input of first operational amplifier 602a. Each of these sequences of voltages corresponds to an attenuation step such that first stage 601a steps the attenuation produced by the attenuator from an intermediate value to a predetermined ending value. A second stage 601b includes a second operational amplifier 602b and a tapped resistor 603b. Tapped resistor 603b includes an input for receiving analog data from first stage 601a, an output coupled to an output of second operational amplifier 602b, and a plurality of taps for selectively presenting a sequence of voltages to a noninverting input of operational amplifier 602b.

Abstract: Audio data processing circuitry 300 includes a plurality of analog inputs 101 for receiving analog audio data and a digital input 105 for receiving digital audio data. A analog mixer 312 mixes analog data received at said plurality of analog inputs 101 to generate a mixed analog audio stream. An analog-to-digital converter 313 converts the mixed analog audio stream to a digital audio stream and a digital mixer 315 mixes digital data received at the digital input 105 with the digital audio stream from the analog mixer 312 to generate a mixed digital audio stream.