Patents by Inventor Bryan D. Boswell

Bryan D. Boswell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8922957
    Abstract: A dynamic switch contact protection circuit and technique to protect a channel switch within an electrical system by limiting transients when the switch is turned on or turned off. The protection circuit comprises switching between a high resistance path and a low resistance path. The high resistance path comprises a resistor. A bypass switch is connected in parallel to the resistor to affect the low resistance path. The protection circuit can connect or disconnect switch cards to the electrical system enabling the creation of a larger switching structure. Disconnected switch cards within a switching structure preserves system bandwidth by limiting capacitive loading. Electing which switch to close last or open first can prolong the length of usage of the switches.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: December 30, 2014
    Assignee: Keysight Technologies, Inc.
    Inventors: Bryan D. Boswell, Robert Wayne Leiby, Steven J. Narciso
  • Patent number: 7977996
    Abstract: A digital pulse generator including a fractional delay filter is provided as having a plurality of step response functions that can be selected on a sample by sample basis by selection of filter coefficients. The step response functions are all identical but each have different group delay. Responsive to an input waveform having leading and trailing edges aligned with a system clock, the fractional delay filter can output the impulse responses as a pulse waveform having respective leading and trailing edges delayed by different respective fractions of a signal clock cycle from the respective leading and trailing edges of the input waveform. The pulse waveform as output can thus have desired pulse width and desired period of repetition with finer edge placement resolution of improved accuracy.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: July 12, 2011
    Assignee: Agilent Technologies, Inc.
    Inventors: David Paul Kjosness, Bryan D. Boswell
  • Publication number: 20090274051
    Abstract: A dynamic switch contact protection circuit and technique to protect a channel switch within an electrical system by limiting transients when the switch is turned on or turned off. The protection circuit comprises switching between a high resistance path and a low resistance path. The high resistance path comprises a resistor. A bypass switch is connected in parallel to the resistor to affect the low resistance path. The protection circuit can connect or disconnect switch cards to the electrical system enabling the creation of a larger switching structure. Disconnected switch cards within a switching structure preserves system bandwidth by limiting capacitive loading. Electing which switch to close last or open first can prolong the length of usage of the switches.
    Type: Application
    Filed: April 30, 2008
    Publication date: November 5, 2009
    Applicant: AGILENT TECHNOLOGIES, INC.
    Inventors: Bryan D. Boswell, Robert W. Leiby, Steven J. Narciso
  • Patent number: 6813646
    Abstract: A method for controlling electronics across an RF barrier is disclosed. The method comprises a serial data control method that requires a limited number of signals passing through an RF barrier and does not require a free running clock. This method uses a processor with an associated serial data control bus that is located external to the RF chamber. An address dependent form of the serial bus passes through an interface to the RF cavity. The processor uses the serial bus to control electronics inside the RF cavity. The control method uses a minimum number of signals passing through the interface to the RF cavity, thereby preserving the RF isolation of the RF cavity from the external environment.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: November 2, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Bryan D. Boswell, Richard E. Warren, Gregory E. Brandes
  • Patent number: 6751570
    Abstract: A system, designed to interact electronically with an RF device, is able to test many types of RF devices and is operable to apply a variety of test inputs to an RF device. The RF device, located within a nest inside an RF enclosure, interacts with the system via a nest electronics component. The nest electronics component, located within the RF enclosure and coupled to a nest interface component and a fixture interface component, supplies power and input test signals to the RF device. The nest electronics component may be configured to interact with a particular RF device, which allows the RF enclosure to used with different types of RF devices. The arrangement of these components allows control and measurement of the RF device to be located as close to it as possible and also allows functionality not required within the RF enclosure to be externally located.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: June 15, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Bryan D. Boswell, Richard E. Warren, Gregory E. Brandes, Terrence Jones
  • Patent number: 6563297
    Abstract: A radio frequency (RF) isolation test device providing versatility and flexibility, along with RF shielding, in the testing of various types of devices. The RF isolation test device provides for ease of accessibility by having a pivoting handle which locks the test device closed and provides for quickly opening of the test device, also assisted through gas springs.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: May 13, 2003
    Assignee: Agilent Technologies, Inc.
    Inventors: Bryan D. Boswell, John L. Bidwell, Russell S. Krajec
  • Publication number: 20030083839
    Abstract: A system, designed to interact electronically with an RF device, is able to test many types of RF devices and is operable to apply a variety of test inputs to an RF device. The RF device, located within a nest inside an RF enclosure, interacts with the system via a nest electronics component. The nest electronics component, located within the RF enclosure and coupled to a nest interface component and a fixture interface component, supplies power and input test signals to the RF device. The nest electronics component may be configured to interact with a particular RF device, which allows the RF enclosure to used with different types of RF devices. The arrangement of these components allows control and measurement of the RF device to be located as close to it as possible and also allows functionality not required within the RF enclosure to be externally located.
    Type: Application
    Filed: October 31, 2001
    Publication date: May 1, 2003
    Inventors: Bryan D. Boswell, Richard E. Warren, Gregory E. Brandes, Terrence Jones
  • Publication number: 20030082959
    Abstract: A method for controlling electronics across an RF barrier is disclosed. The method comprises a serial data control method that requires a limited number of signals passing through an RF barrier and does not require a free running clock. This method uses a processor with an associated serial data control bus that is located external to the RF chamber. An address dependent form of the serial bus passes through an interface to the RF cavity. The processor uses the serial bus to control electronics inside the RF cavity. The control method uses a minimum number of signals passing through the interface to the RF cavity, thereby preserving the RF isolation of the RF cavity from the external environment.
    Type: Application
    Filed: October 31, 2001
    Publication date: May 1, 2003
    Inventors: Bryan D. Boswell, Richard E. Warren, Gregory E. Brandes
  • Patent number: 6545459
    Abstract: A radio frequency (RF) isolation test device providing versatility and flexibility, along with RF shielding, in the testing of various types of devices. The test device includes a removable plate providing connections for access to a device under test when located within the test device. It also includes a base plate for use in securing a removable nest plate within the test device to accommodate testing of various configurations of devices under test.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: April 8, 2003
    Assignee: Agilent Technologies, Inc.
    Inventors: Bryan D. Boswell, John L. Bidwell, Russell S. Krajec
  • Patent number: 6469495
    Abstract: A radio frequency (RF) isolation test device providing versatility and flexibility, along with RF shielding, in the testing of various types of devices. The test device includes a removable plate providing connections for access to a device under test when located within the test device. It also includes a base plate for use in securing a removable nest plate within the test device to accommodate testing of various configurations of devices under test.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: October 22, 2002
    Assignee: Agilent Technologies, Inc.
    Inventors: Bryan D. Boswell, John L Bidwell, Russell S. Krajec
  • Publication number: 20020074993
    Abstract: A radio frequency (RF) isolation test device providing versatility and flexibility, along with RF shielding, in the testing of various types of devices. The test device includes a removable plate providing connections for access to a device under test when located within the test device. It also includes a base plate for use in securing a removable nest plate within the test device to accommodate testing of various configurations of devices under test.
    Type: Application
    Filed: October 15, 2001
    Publication date: June 20, 2002
    Inventors: Bryan D. Boswell, John L. Bidwell, Russell S. Krajec
  • Patent number: 6377038
    Abstract: A radio frequency (RF) isolation test device providing versatility and flexibility, along with RF shielding and a low resonance test environment, in the testing of various types of devices. The RF isolation test device includes a “box within a box” configuration. An inner box provides for shielding of a device under test and for reducing interference from reflections from RF energy from the device to provide a low resonance test environment. An outer box provides for primary shielding of the device under test from external RF energy.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: April 23, 2002
    Assignee: Agilent Technologies, Inc.
    Inventors: Bryan D. Boswell, John L Bidwell, Russell S. Krajec
  • Patent number: 6291978
    Abstract: A method for testing node interconnection on a circuit board. The method utilizes an automated test system having at least one test channel, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. During a node interconnection test, the driver of a first test channel applies a test signal to a selected node of the plurality of nodes. A predetermined amount of time after application of the test signal, the receiver of the first test channel reads a node voltage of the selected node. The node voltage is then compared to a predetermined threshold voltage of the receiver of the first test channel, and the result of the comparison is an indication as to whether the selected node is coupled to ground.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: September 18, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 6191570
    Abstract: A method for testing node isolation on a circuit board. The method utilizes an automated test system having a plurality of test channels, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver, to a number of switches, and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. The number of switches are configured to selectively couple the first output and second input to ground. During a node isolation test, each node of a test node group is coupled to one of the test channels. But for a selected node of the test node group, each node of the test node group is coupled to ground via the number of switches of the test channels coupled to the nodes.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: February 20, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 6051979
    Abstract: A method for testing node interconnection on a circuit board. The method utilizes an automated test system having at least one test channel, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. During a node interconnection test, a first selected node is coupled to a first test channel, and it is determined whether the first selected node is connected to ground. If the first selected node is not connected to ground, a second selected node is connected to ground; a test signal is applied to the first selected node via the digital driver of the first test channel; and it is determined whether the first selected node is connected to the second selected node.
    Type: Grant
    Filed: July 25, 1999
    Date of Patent: April 18, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 5977775
    Abstract: An automatic circuit board tester for testing for shorts, opens, and interconnected pins or nodes on a circuit board. The tester first classifies the nodes as being in one of three categories based upon the design of the board and the intended interconnection of the nodes. The categories of nodes are: (1) connected to ground; (2) interconnected to all other nodes in the test group; or (3) isolated from all other nodes. The circuit board tester has a testhead containing a plurality of test channels, each configured to be coupled to a node on the circuit board. The testhead utilizes a digital signal from a digital driver to drive the node, at a predetermined voltage and a digital receiver to read the node voltage to determine if it is coupled to ground. Each test channel also includes a switch to connect the digital driver and receiver to the test node as well as a ground switch to selectively couple the node to ground.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: November 2, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 5504432
    Abstract: An automatic circuit board tester for testing for shorts, opens, and interconnected pins or nodes on a circuit board. The tester first classifies the nodes as being in one of three categories based upon the design of the board and the intended interconnection of the nodes. The categories of nodes are: (1) connected to ground; (2) interconnected to all other nodes in the test group; or (3) isolated from all other nodes. The circuit board tester has a testhead containing a plurality of test channels, each configured to be coupled to a node on the circuit board. The testhead utilizes a digital signal from a digital driver to drive the node at a predetermined voltage and a digital receiver to read the node voltage to determine if it is coupled to ground. Each test channel also includes a switch to connect the digital driver and receiver to the test node as well as a ground switch to selectively couple the node to ground.
    Type: Grant
    Filed: August 31, 1993
    Date of Patent: April 2, 1996
    Assignee: Hewlett-Packard Company
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer