Patents by Inventor Bryan D. Hornung
Bryan D. Hornung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11726914Abstract: Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.Type: GrantFiled: August 17, 2022Date of Patent: August 15, 2023Assignee: Micron Technology, Inc.Inventors: Dean Walker, Bryan D. Hornung, Tony M. Brewer, David M. Patrick, Christopher A. Baronne
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Patent number: 11714704Abstract: Systems, apparatuses, and methods related to modified checksum data using a poison data indictor. An example method can include receiving a first set of bits including data and a second set of at least one bit indicating whether the first set of bits includes one or more erroneous or corrupted bits. A first checksum can be generated that is associated with the first set of bits. A second checksum can be generated using the first checksum and the second set of at least one bit. The first set of bits and the second checksum can be written to an array of a memory device. A comparison of the first checksum and the second checksum can indicate whether the first set of bits includes the at least one or more erroneous or corrupted bits.Type: GrantFiled: August 15, 2022Date of Patent: August 1, 2023Assignee: Micron Technology, Inc.Inventors: Tony M. Brewer, Bryan D. Hornung
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Publication number: 20230043177Abstract: Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.Type: ApplicationFiled: August 17, 2022Publication date: February 9, 2023Inventors: Dean Walker, Bryan D. Hornung, Tony M. Brewer, David M. Patrick, Christopher A. Baronne
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Publication number: 20220391282Abstract: Systems, apparatuses, and methods related to modified checksum data using a poison data indictor. An example method can include receiving a first set of bits including data and a second set of at least one bit indicating whether the first set of bits includes one or more erroneous or corrupted bits. A first checksum can be generated that is associated with the first set of bits. A second checksum can be generated using the first checksum and the second set of at least one bit. The first set of bits and the second checksum can be written to an array of a memory device. A comparison of the first checksum and the second checksum can indicate whether the first set of bits includes the at least one or more erroneous or corrupted bits.Type: ApplicationFiled: August 15, 2022Publication date: December 8, 2022Inventors: Tony M. Brewer, Bryan D. Hornung
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Publication number: 20220292018Abstract: Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.Type: ApplicationFiled: March 10, 2021Publication date: September 15, 2022Inventors: Dean Walker, Bryan D. Hornung, Tony M. Brewer, David M. Patrick, Christopher A. Baronne
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Patent number: 11442858Abstract: Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.Type: GrantFiled: March 10, 2021Date of Patent: September 13, 2022Assignee: Micron Technology, Inc.Inventors: Dean Walker, Bryan D. Hornung, Tony M. Brewer, David M. Patrick, Christopher A. Baronne
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Patent number: 11416331Abstract: Systems, apparatuses, and methods related to modified checksum data using a poison data indictor. An example method can include receiving a first set of bits including data and a second set of at least one bit indicating whether the first set of bits includes one or more erroneous or corrupted bits. A first checksum can be generated that is associated with the first set of bits. A second checksum can be generated using the first checksum and the second set of at least one bit. The first set of bits and the second checksum can be written to an array of a memory device. A comparison of the first checksum and the second checksum can indicate whether the first set of bits includes the at least one or more erroneous or corrupted bits.Type: GrantFiled: December 9, 2020Date of Patent: August 16, 2022Assignee: Micron Technology, Inc.Inventors: Tony M. Brewer, Bryan D. Hornung
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Publication number: 20220179735Abstract: Systems, apparatuses, and methods related to modified checksum data using a poison data indictor. An example method can include receiving a first set of bits including data and a second set of at least one bit indicating whether the first set of bits includes one or more erroneous or corrupted bits. A first checksum can be generated that is associated with the first set of bits. A second checksum can be generated using the first checksum and the second set of at least one bit. The first set of bits and the second checksum can be written to an array of a memory device. A comparison of the first checksum and the second checksum can indicate whether the first set of bits includes the at least one or more erroneous or corrupted bits.Type: ApplicationFiled: December 9, 2020Publication date: June 9, 2022Inventors: Tony M. Brewer, Bryan D. Hornung
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Patent number: 5905869Abstract: A multi-processor multi-node system having access to a low skew clock to synchronize processing events. This system uses a SCI network to distribute a low skew signal to synchronize the time of century clock counters on the different nodes. These counters are periodically synchronized with a signal from a selected master counter, so that all nodes will maintain approximately equal counter values. A single bit in a SCI header of send, echo, or idle packet is routed to all nodes via a SCI ring. Since the bit is inserted in existing packets, the creation of a special synchronizing packet is not required. Moreover, since the bit travels over existing lines, additional signal paths or extra wire are not needed.Type: GrantFiled: September 27, 1996Date of Patent: May 18, 1999Assignee: Hewlett-Packard, Co.Inventors: Bryan D. Hornung, Tony M. Brewer
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Patent number: 5898827Abstract: A multi-dimensional node or processor arrangement allows a similar number of nodes in a linear array to be arranged in a more compact form, thus overcoming a latency problem in communications between the most distant nodes/processors. The multi-dimensional arrangement also allows for multiple paths between nodes. This feature greatly improves survivability of the system, such that when one node dies there is always at least one other path that is available to get to the other nodes in the system. Thus, the system can continue to run and only the resources of the one node that died are lost. A first set of routing rules governs the migration of communications between a source node and a destination node around the node array when all of the nodes are functioning. A secondary set of rules displaces or modifies the first set when a node is not functioning.Type: GrantFiled: September 27, 1996Date of Patent: April 27, 1999Assignee: Hewlett-Packard Co.Inventors: Bryan D. Hornung, Bryan D. Marietta