Abstract: A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.

Abstract: A processing system includes a plurality of coherency domains and a plurality of coherency agents. Each coherency agent is associated with at least one of the plurality of coherency domains. At a select coherency agent of the plurality of coherency agents, an address translation for a coherency message is performed using a first memory address to generate a second memory address. A select coherency domain of the plurality of coherency domains associated with the coherency message is determined at the select coherency agent based on the address translation. The coherency message and a coherency domain identifier of the select coherency domain are provided by the select coherency agent to a coherency interconnect for distribution to at least one of the plurality of coherency agents based on the coherency domain identifier.

Abstract: A digital data system employs multiple error protection mechanisms on messages that pass along a link interconnect fabric from one node or device to another node or device. The nodes may be end points (such as processor or storage units), or may be intermediate devices or branch points (such as routers or switches in the interconnect fabric). The interconnect fabric comprises a set of one or more routers, switches, electrical, optical, electroptical or other links along which messages are passed. Messages are packets having a defined format including, e.g., a header portion, typically with source and target addresses, and codes indicating message-type or other information, followed by one or more data or other fields. A first node (“sending” node) of a digital data system as described sends a data transmission comprising one or more message packets to a second node (“receiving” node) over a link of a fabric as described above.

Abstract: A digital data system comprises a plurality of links for passing messages between nodes, which may be end points such as memory or processing units, or intermediate or branch points such as routers or other devices in the system. A link level flow control is implemented by control symbols passed between adjacent nodes on a link to efficiently regulate message burden on the link. The control symbols may be embedded within in a message packet to quickly effect control on a link—such as reducing data flow, requesting retransmission of corrupted data, or other intervention—without disruption of the ongoing packet reception. A control symbol may be recognized within the packet by a flag bit, a marker such as a transition in a signal, or a combination of characteristics. The control symbol may be a short word, having a control action identifier code at defined bit positions to indicate the desired link-level control function.

Abstract: A data communication system (10) has a plurality of devices (12, 14, 17) which communicate by transmitting information packets having order tags which are processed by an input unit (60) and an output unit (30) in each device. A packet is sent from a transmitting device to a receiving device having an ordering tag wherein both devices are initially order synchronized by starting with the same ordering tag value. Packet transmissions are forced to occur in an order which follows a predetermined ordering of order values which the ordering tags can have. If the receiving device does not receive a packet having the correct order tag value or if a transmission error is detected, the receiving device tells the transmitting device to resend the packet. Any subsequent outstanding transmissions are discarded. Packet ordering and verification occurs at each device-to-device connection.

Abstract: A multi-processing system (10) comprises a plurality of groups, each having an arbitrary number of processing systems (11, 12). Memory coherency may or may not be established within any particular group. However, each group is intentionally arranged by functionality so that memory coherency, if implemented, only needs to be maintained within the group. Information transfers between two groups are therefore non-coherent by definition. Memory coherency implementation is significantly reduced in the system. A transaction format utilizes group and processing system identifiers to implement the simplified coherency scheme.

Abstract: A multi-processing system (50) utilizes an interconnect fabric (59) for coupling endpoint devices (52, 54, 56, 66, 67). Bus control functions are managed in a method which is bus protocol independent. Each of the endpoint devices and the fabric function by specific rules to transfer data having a priority. Within the interconnect, higher priority data transfers take precedence of servicing, and for equal priority data the data is serviced first-in, first-out. Requests of endpoint devices that require a response can not be sent at the highest priority. Endpoint devices may not allow the acceptance of data to be contingent on outputting data of equal or lesser priority than the priority of the incoming data. Transaction priority, ordering and deadlocks are efficiently handled without the interconnect fabric needing to implement a set of bus protocol rules. Within the endpoint devices, additional rules related to ordering may be implemented.

Abstract: A data communication system (10) has a plurality of devices (12,14,17) which communicate by transmitting information packets having order tags which are processed by an input unit (60) and an output unit (30) in each device. A packet is sent from a transmitting device to a receiving device having an ordering tag wherein both devices are initially order synchronized by starting with the same ordering tag value. Packet transmissions are forced to occur in an order which follows a predetermined ordering of order values which the ordering tags can have. If the receiving device does not receive a packet having the correct order tag value or if a transmission error is detected, the receiving device tells the transmitting device to resend the packet. Any subsequent outstanding transmissions are discarded. Packet ordering and verification occurs at each device-to-device connection.

Abstract: A multi-processing system (50) utilizes an interconnect fabric (59) for coupling endpoint devices (52, 54, 56, 66, 67). Bus control functions are managed in a method which is bus protocol independent. Each of the endpoint devices and the fabric function by specific rules to transfer data having a priority. Within the interconnect, higher priority data transfers take precedence of servicing, and for equal priority data the data is serviced first-in, first-out. Requests of endpoint devices that require a response can not be sent at the highest priority. Endpoint devices may not allow the acceptance of data to be contingent on outputting data of equal or lesser priority than the priority of the incoming data. Transaction priority, ordering and deadlocks are efficiently handled without the interconnect fabric needing to implement a set of bus protocol rules. Within the endpoint devices, additional rules related to ordering may be implemented.

Abstract: A multi-processing system (10) comprises a plurality of groups, each having an arbitrary number of processing systems (11, 12). Memory coherency may or may not be established within any particular group. However, each group is intentionally arranged by functionality so that memory coherency, if implemented, only needs to be maintained within the group. Information transfers between two groups are therefore non-coherent by definition. Memory coherency implementation is significantly reduced in the system. A transaction format utilizes group and processing system identifiers to implement the simplified coherency scheme.

Abstract: A bump-bonded multi-chip flip-chip device (100) is formed by manufacturing a mother chip (102) having a first set (207) of bumps (212) and a second set (209) of bump contacts (210). A daughter chip (104) is also formed which has conductive bumps (312). The daughter chip (104) and the mother chip (102) are placed face-to-face and contact is made between the daughter chips bumps (312) and the mother chips bump contact regions (210). After interconnection of the daughter chip (104) and the mother chip (102), the mother chip (102) is contacted to an IC package (106) using the bumps (212). The package (106) uses a plurality of metallic layers interconnected selectively by conductive vias in order to route signals between the mother chip (102), the daughter chip (104), and external terminals (112) of the package (106).

Abstract: A multi-dimensional node or processor arrangement allows a similar number of nodes in a linear array to be arranged in a more compact form, thus overcoming a latency problem in communications between the most distant nodes/processors. The multi-dimensional arrangement also allows for multiple paths between nodes. This feature greatly improves survivability of the system, such that when one node dies there is always at least one other path that is available to get to the other nodes in the system. Thus, the system can continue to run and only the resources of the one node that died are lost. A first set of routing rules governs the migration of communications between a source node and a destination node around the node array when all of the nodes are functioning. A secondary set of rules displaces or modifies the first set when a node is not functioning.

Abstract: A method (600, 700) and apparatus (402) for controlling a memory device, such as a synchronous dynamic random access memory (404), includes a user-programmable register containing a new parameter, PRECHARGE DELAY TIME. A memory controller (402) uses the parameter to set a minimum limit through which each page is kept open after an initial access. Subsequent access to the same page cause the controller to reset the limit, thereby extending the open page. Accesses to different pages, refresh operations, and maximum row address strobe parameters can force the page closed. A user can tune the PRECHARGE DELAY TIME to keep pages open through the time period in which it is likely that additional accesses will be to the same page. Conversely, open pages can be closed after that time period is exceeded. In both cases, the memory device will be ready for a subsequent access with minimum latency.

Abstract: Memory control circuitry is provided which includes circuitry for generating a sequence of gray code values. Counter circuitry is coupled to the gray code circuitry and controls the duration of assertion of each of the generated gray code values. Bus circuitry is also coupled to the gray code circuitry for transmitting the gray code values generated by circuitry. Programmable logic array circuitry is also coupled to the bus circuitry for transmitting, receiving and decoding each of the gray code values and providing at least one memory control signal in response.

Abstract: Circuitry 300 is disclosed for isolating faults in a path 304 transmitting data words each having at least one data bit and at least one parity bit. Circuitry 300 includes a plurality of exclusive-OR gates 303 each having a first input coupled to the data path 304 for receiving a bit of a one of the data words being transmitted along path 304. A plurality of multiplexers 305 are also provided, each multiplexer 305 including a first input coupled to an output of a corresponding one of the exclusive-OR gates 303 and a control signal input for receiving a control signal. A plurality of registers 306 have an input coupled to an output of a corresponding one of the multiplexers 305 and an output coupled to a second input of a corresponding one of the exclusive-OR gates 303 and a second input of the corresponding one of the multiplexers 305.

Abstract: A circuit is disclosed for reducing the number of signal lines passing through a connector (205) comprised of a shift register coupled to a plurality of input data lines and half as many output data lines. When a load signal is received, the shift register latches the data from the input data lines and immediately transmits half of the data to the output data lines and through the connector. When the shift register receives a shift signal, the other half of the data is shifted onto the same output lines and pass through the connector to achieve a two-to-one multiplexing function.