Patents by Inventor Bryan D. Preble

Bryan D. Preble has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170187399
    Abstract: Embodiments of single-ended and differential output driver circuits include one or more complementary data switch pairs, each coupled to a T-coil. Each complementary data switch pair is coupled between a voltage source and a ground reference node, and each complementary data switch pair includes complementary transistors, each with a control terminal, a first current conducting terminal, and a second current conducting terminal. In each pair, the first current conducting terminals of the complementary transistors are coupled together at an output node, and the control terminals of the complementary transistors are configured to receive an input signal. A T-coil is coupled to the output node, and includes a first coil coupled between the output node and an output terminal, and a second coil coupled between the output node and a termination. A mutual inductance is present between the first and second coils during operation of the output driver circuit.
    Type: Application
    Filed: December 29, 2015
    Publication date: June 29, 2017
    Inventors: Earl K. Hunter, BRYAN D. PREBLE
  • Patent number: 7593202
    Abstract: An integrated circuit (300/400) includes first and second power domains and a bank of input/output (I/O) cells (305/405) coupled to the first and second power domains. The bank of I/O cells (305/405) includes a first plurality of active clamps (374/445) for the first power domain and a second plurality of active clamps (384/425) for the second power domain wherein the first (374/445) and second (384/425) pluralities of active clamps overlap along the bank of I/O cells. According to one aspect each of the plurality of input/output cells (420, 440) has a bonding pad (421, 441) for receiving an output signal referenced to a respective first power domain, and at least one ESD protection element (425, 445) for a respective second power domain. According to another aspect, each of the plurality of input/output cells (420, 440) has a bonding pad (421, 441) for receiving a respective output signal and at least one ESD protection element for each of a first power domain and a second power domain.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: September 22, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael G. Khazhinsky, Martin J. Bayer, James W. Miller, Bryan D. Preble