Patents by Inventor Bryan D. Sendelweck

Bryan D. Sendelweck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FORMING RECESSED STRUCTURE WITH LIQUID-DEPOSITED SOLUTION
    Publication number: 20150144883
    Abstract: A damascene approach is used to form a recessed structure in a substrate for receiving liquid-deposited solution, such as a carbon nanotube (CNT) solution. The liquid-deposited solution is built-up in the recessed structure, simplifying the coating process and providing a more uniform thickness of the liquid-deposited layer.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: Atmel Corporation
    Inventor: Bryan D. Sendelweck
  • Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device
    Patent number: 8138578
    Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: March 20, 2012
    Assignee: Atmel Corporation
    Inventors: Gayle W. Miller, Jr., Bryan D. Sendelweck
  • LOCOS self-aligned twin well with a co-planar silicon surface
    Patent number: 7642181
    Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include masking a first portion of the device such that a second portion of the device is exposed. A sacrificial layer has a first portion on the first portion of the device and a second portion on the second portion of the device. In one aspect, an oxidation stop layer may be below the sacrificial layer. The method and system include implanting a first well in the second portion of the device, exposing the first portion of the device after the first well is implanted, and oxidizing the second portion of sacrificial layer after the exposing. The method and system further include implanting the second well in the first portion of the device after the oxidizing and planarizing the device after the second well is implanted.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: January 5, 2010
    Assignee: Atmel Corporation
    Inventors: Gayle W. Miller, Jr., Irwin D. Rathbun, Bryan D. Sendelweck, Thomas S. Moss, III
  • METHOD AND SYSTEM FOR CREATING SELF-ALIGNED TWIN WELLS WITH CO-PLANAR SURFACES IN A SEMICONDUCTOR DEVICE
    Publication number: 20090206452
    Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.
    Type: Application
    Filed: April 20, 2009
    Publication date: August 20, 2009
    Applicant: Atmel Corporation
    Inventors: Gayle W. Miller, JR., Bryan D. Sendelweck
  • Method for forming a self-aligned twin well region with simplified processing
    Patent number: 7541250
    Abstract: A method for forming a self-aligned twin well region is provided. The method includes implanting a first well type doping species into the DHL such that its distribution remains stopped in the DHL above the silicon substrate, etching away a portion of the DHL using a photoresist mask, implanting a second well type doping species into the portions of the silicon substrate exposed by the etching, and moving a portion of the first well type doping species into the silicon substrate.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: June 2, 2009
    Assignee: Atmel Corporation
    Inventors: Gayle W. Miller, Jr., Bryan D. Sendelweck
  • Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device
    Patent number: 7521312
    Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: April 21, 2009
    Assignee: Atmel Corporation
    Inventors: Gayle W. Miller, Jr., Bryan D. Sendelweck
  • Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device
    Publication number: 20080166862
    Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 10, 2008
    Inventors: Gayle W. Miller, Bryan D. Sendelweck