Abstract: According to one embodiment of the invention, a memory circuit operable to assume a standby mode is provided. A memory circuit includes a transistor comprising a gate and a bulk. The bulk is at a retention voltage level. The memory circuit also includes a first node and a second node that are coupled to each other by the transistor. The first node is operable to assume a higher voltage level than the second node in response to an initiation of the standby mode. The memory circuit also includes a third node coupled to the gate of the transistor. The third node is operable to assume a voltage approximately equal to the retention voltage in response to an initiation of the standby mode. The transistor is operable to reduce any direct current flow between the first node and the second node in response to a rise in voltage at the third node to a voltage approximately equal to the retention voltage.

Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Abstract: A method of reducing power supply current transients in a memory array caused by a simultaneous change in logic state of numerous CMOS digital circuits during a memory write cycle. Write driver enable signals (ENT, ENC) and bitcell enable signals (WBC1-WBC24) are sequentially delayed in time during the write cycle through use of the propagation delay of inverters (INV1-INV24-7). The sequential time delay reduces the number of circuits that are simultaneously changing logic state at any given time during the write cycle. The power supply current transient is transformed from a single, large change in current to a series of smaller changes displaced in time from each other during the write cycle. The ground bounce of the power supply network attributed to the current transient is significantly reduced, such change in ground potential being directly related to the magnitude of the current transient and its rate of change with respect to time.

Abstract: The write port circuits of a static memory cell includes a first conditional conduction path between a first output of the latch and ground active if and only if both a word line input and a write data true bit line input receive active signals. The write port circuit includes a second conditional conduction path between a second output of the latch and ground active if and only if both the word line and a write data complement bit line receive active signals. The first and second conditional conduction paths may be formed by a series connection of the source-drain paths of two transistors. In each conditional conduction path the gate of a first transistor receives a corresponding column signal and the gate of a second transistor is connected to the word line. The first and second transistors for each conduction path may be N-channel MOS transistors formed in a single N-type region. The first and second transistors forming the conditional conduction paths may be in either order.

Abstract: The low power data line and method may comprise a line (30, 102) connecting a plurality of devices (60, 104) to an output (32, 104). The devices (60, 104) may be independently accessed to provide data to the output (32) along the line (30, 102). A switch (40, 120) may be disposed in the line (30, 102) to selectively disconnect a segment (52, 132) of the line (30, 102) connected to at least one of the devices (60, 104) from the output (32).

Abstract: This invention is useful in column multiplexed memories, particularly static random access memories (SRAM) used in application specific integrated circuits (ASIC) . These column multiplexed memories include memory cells disposed in rows and columns. For writes all the bitlines are connected to a bias generator. The bias generator uses first P-channel field effect transistor and a first N-channel field effect transistor connected in series with their junction connected to the bitline. The bias generator is driven by a bias enable pulse that is active for a short time before the write time. Normally these field effect transistors are biased OFF by a second P-channel field effect transistor and a second N-channel field effect transistor. Another pair of N-channel field effect transistors connect the bases of the first P-channel field effect transistor and the first N-channel field effect transistor together to the bitline when the bias enable pulse is active.

Abstract: A gate array structure includes a plurality of transistors (21-47) interconnected to form a two-bit memory cell. First and second interconnected transistors of the plurality are respectively provided in adjacent base sites (51, 53) of the gate array structure.