Patents by Inventor Bryan Darrell Bowyer
Bryan Darrell Bowyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8522197Abstract: A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. Each of the hierarchical design schedule blocks includes control steps numbered relative to the block. The scheduling information also includes a hierarchical list of scheduled operations for the design. The hierarchical list emphasizes which operations are associated with which nested blocks. The scheduling information further includes pseudo-operation icons that are easily differentiated from real operation icons in the hierarchical Gantt chart.Type: GrantFiled: November 30, 2010Date of Patent: August 27, 2013Assignee: Mentor Graphics CorporationInventors: Peter Pius Gutberlet, Simon Joshua Waters, Bryan Darrell Bowyer
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Publication number: 20110138348Abstract: A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. Each of the hierarchical design schedule blocks includes control steps numbered relative to the block. The scheduling information also includes a hierarchical list of scheduled operations for the design. The hierarchical list emphasizes which operations are associated with which nested blocks. The scheduling information further includes pseudo-operation icons that are easily differentiated from real operation icons in the hierarchical Gantt chart.Type: ApplicationFiled: November 30, 2010Publication date: June 9, 2011Inventors: Peter Pius Gutberlet, Simon Joshua Waters, Bryan Darrell Bowyer
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Patent number: 7844944Abstract: A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. Each of the hierarchical design schedule blocks includes control steps numbered relative to the block. The scheduling information also includes a hierarchical list of scheduled operations for the design. The hierarchical list emphasizes which operations are associated with which nested blocks. The scheduling information further includes pseudo-operation icons that are easily differentiated from real operation icons in the hierarchical Gantt chart.Type: GrantFiled: September 8, 2006Date of Patent: November 30, 2010Assignee: Mentor Graphics CorporationInventors: Peter Pius Gutberlet, Simon Joshua Waters, Bryan Darrell Bowyer
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Patent number: 7831938Abstract: A behavioral synthesis tool that allows a designer to design an integrated circuit using a generic programming language, such as ANSI C or C++, without the need to include timing information into the source code. In one aspect, the source code is read into the behavioral synthesis tool and the user may dynamically allocate interface resources to the design. In another aspect, the dynamic allocation is accomplished through user input, such as a GUI, a command line, or a file. In another aspect, the behavioral synthesis tool automatically analyzes variables in the source code description and assigns the variables to interface resources. In yet another aspect, the variables and interface resources associated with the variables may be displayed in a hierarchical format in a GUI. In still another aspect, the GUI may allow for expanding and collapsing of different layers in the hierarchy. The GUI may also allow for drag-and-drop operations for modifying the allocation of variables to interface resources.Type: GrantFiled: November 21, 2007Date of Patent: November 9, 2010Assignee: Mentor Graphics CorporationInventors: Bryan Darrell Bowyer, Peter Pius Gutberlet, Simon Joshua Waters
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Patent number: 7712050Abstract: A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. Each of the hierarchical design schedule blocks includes control steps numbered relative to the block. The scheduling information also includes a hierarchical list of scheduled operations for the design. The hierarchical list emphasizes which operations are associated with which nested blocks. The scheduling information further includes pseudo-operation icons that are easily differentiated from real operation icons in the hierarchical Gantt chart.Type: GrantFiled: September 8, 2006Date of Patent: May 4, 2010Inventors: Peter Pius Gutberlet, Simon Joshua Waters, Bryan Darrell Bowyer
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Patent number: 7412684Abstract: Methods and apparatus for analyzing and processing loops within an integrated circuit design are described. According to one embodiment, the processing comprises unrolling loops. In another embodiment, the processing comprises pipelining loops. In yet another embodiment, the processing comprises merging loops. In any of the disclosed embodiments, loops comprise independent loops, dependent loops or some combination thereof. Other embodiments for processing loops are disclosed, as well as integrated circuits and circuit design databases resulting from the disclosed methods. Computer-executable media storing instructions for performing the disclosed methods are also disclosed.Type: GrantFiled: November 10, 2004Date of Patent: August 12, 2008Inventors: Peter Pius Gutberlet, Andres R. Takach, Bryan Darrell Bowyer
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Publication number: 20080172646Abstract: A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate variables or arrays to memory resources without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find arrays for each process. The arrays are then listed in a graphical user interface (GUI). The GUI allows the designer to create memory resources, specifying the type of memory, the packing mode, etc. The designer is also provided the ability to vary the format among a plurality of formats used to pack arrays to memory during the memory packing process. Upon completion of modifying the memory allocation, the designer saves the changes and such changes are effectuated by automatically updating the synthesis intermediate format.Type: ApplicationFiled: December 17, 2007Publication date: July 17, 2008Inventors: Shiv Prakash, Bryan Darrell Bowyer, Peter Pius Gutberlet
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Patent number: 7310787Abstract: A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate variables or arrays to memory resources without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find arrays for each process. The arrays are then listed in a graphical user interface (GUI). The GUI allows the designer to create memory resources, specifying the type of memory, the packing mode, etc. The designer is also provided the ability to vary the format among a plurality of formats used to pack arrays to memory during the memory packing process. Upon completion of modifying the memory allocation, the designer saves the changes and such changes are effectuated by automatically updating the synthesis intermediate format.Type: GrantFiled: March 7, 2003Date of Patent: December 18, 2007Inventors: Shiv Prakash, Bryan Darrell Bowyer, Peter Pius Gutberlet
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Patent number: 7302670Abstract: A behavioral synthesis tool that allows a designer to design an integrated circuit using a generic programming language, such as ANSI C or C++, without the need to include timing information into the source code. In one aspect, the source code is read into the behavioral synthesis tool and the user may dynamically allocate interface resources to the design. In another aspect, the dynamic allocation is accomplished through user input, such as a GUI, a command line, or a file. In another aspect, the behavioral synthesis tool automatically analyzes variables in the source code description and assigns the variables to interface resources. In yet another aspect, the variables and interface resources associated with the variables may be displayed in a hierarchical format in a GUI. In still another aspect, the GUI may allow for expanding and collapsing of different layers in the hierarchy. The GUI may also allow for drag-and-drop operations for modifying the allocation of variables to interface resources.Type: GrantFiled: December 5, 2002Date of Patent: November 27, 2007Inventors: Bryan Darrell Bowyer, Peter Pius Gutberlet, Simon Joshua Waters
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Patent number: 7168059Abstract: A tool is disclosed that allows a hardware designer using a behavioral synthesis tool to view a calculated execution time for a group of related loops identified in source code describing a hardware design circuit. Further, a designer can then interactively unroll and/or pipeline a selected loop without having to modify the source code description of the circuit. Using a graphical user interface (GUI), the designer can modify the loop design easily and see the results of the new loop configuration without having to generate the RTL code, perform RTL synthesis, etc. For example, the designer can readily view the relative loop execution time of the circuit to better determine whether the design is acceptable. Additionally, the designer can execute an area-versus-latency analysis, and, if the analysis is not satisfactory, the designer can unroll and or pipeline selected loops using the GUI.Type: GrantFiled: April 19, 2002Date of Patent: January 23, 2007Inventors: Bryan Darrell Bowyer, David Gaines Burnette, Ian Andrew Guyler
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Patent number: 7120879Abstract: A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. Each of the hierarchical design schedule blocks includes control steps numbered relative to the block. The scheduling information also includes a hierarchical list of scheduled operations for the design. The hierarchical list emphasizes which operations are associated with which nested blocks. The scheduling information further includes pseudo-operation icons that are easily differentiated from real operation icons in the hierarchical Gantt chart.Type: GrantFiled: July 31, 2001Date of Patent: October 10, 2006Inventors: Peter Pius Gutberlet, Simon Joshua Waters, Bryan Darrell Bowyer
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Publication number: 20040111692Abstract: A behavioral synthesis tool that allows a designer to design an integrated circuit using a generic programming language, such as ANSI C or C++, without the need to include timing information into the source code. In one aspect, the source code is read into the behavioral synthesis tool and the user may dynamically allocate interface resources to the design. In another aspect, the dynamic allocation is accomplished through user input, such as a GUI, a command line, or a file. In another aspect, the behavioral synthesis tool automatically analyzes variables in the source code description and assigns the variables to interface resources. In yet another aspect, the variables and interface resources associated with the variables may be displayed in a hierarchical format in a GUI. In still another aspect, the GUI may allow for expanding and collapsing of different layers in the hierarchy. The GUI may also allow for drag-and-drop operations for modifying the allocation of variables to interface resources.Type: ApplicationFiled: December 5, 2002Publication date: June 10, 2004Applicant: Mentor Graphics Corp.Inventors: Bryan Darrell Bowyer, Peter Pius Gutberlet, Simon Joshua Waters
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Publication number: 20030172055Abstract: A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate variables or arrays to memory resources without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find arrays for each process. The arrays are then listed in a graphical user interface (GUI). The GUI allows the designer to create memory resources, specifying the type of memory, the packing mode, etc. The designer is also provided the ability to vary the format among a plurality of formats used to pack arrays to memory during the memory packing process. Upon completion of modifying the memory allocation, the designer saves the changes and such changes are effectuated by automatically updating the synthesis intermediate format.Type: ApplicationFiled: March 7, 2003Publication date: September 11, 2003Applicant: Mentor Graphics CorporationInventors: Shiv Prakash, Bryan Darrell Bowyer, Peter Pius Gutberlet
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Publication number: 20030033039Abstract: A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. Each of the hierarchical design schedule blocks includes control steps numbered relative to the block. The scheduling information also includes a hierarchical list of scheduled operations for the design. The hierarchical list emphasizes which operations are associated with which nested blocks. The scheduling information further includes pseudo-operation icons that are easily differentiated from real operation icons in the hierarchical Gantt chart.Type: ApplicationFiled: July 31, 2001Publication date: February 13, 2003Applicant: Mentor Graphics CorporationInventors: Peter Pius Gutberlet, Simon Joshua Waters, Bryan Darrell Bowyer
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Publication number: 20030005404Abstract: A tool is disclosed that allows a hardware designer using a behavioral synthesis tool to view a calculated execution time for a group of related loops identified in source code describing a hardware design circuit. Further, a designer can then interactively unroll and/or pipeline a selected loop without having to modify the source code description of the circuit. Using a graphical user interface (GUI), the designer can modify the loop design easily and see the results of the new loop configuration without having to generate the RTL code, perform RTL synthesis, etc. For example, the designer can readily view the relative loop execution time of the circuit to better determine whether the design is acceptable. Additionally, the designer can execute an area-versus-latency analysis, and, if the analysis is not satisfactory, the designer can unroll and or pipeline selected loops using the GUI.Type: ApplicationFiled: April 19, 2002Publication date: January 2, 2003Applicant: Mentor GraphicsInventors: Bryan Darrell Bowyer, David Gaines Burnette, Ian Andrew Guyler