Abstract: In one embodiment, the present invention includes a method for receiving an incoming packet in a packet buffer and associating it with a flow identifier. Based on the flow identifier, a core to which the incoming packet is to be directed may be determined, and a power management hint can be transmitted to cause the core to be powered up. Other embodiments are described and claimed.

Abstract: A disk array redundancy controller ensures integrity of a mirrored or RAID storage array supporting a host system and minimizes recovery time responsive to a storage volume failure by traversing caches of recently written blocks to identify partially flushed stripes of data and recovering the inconsistent stripes on each of the storage volumes based on a master copy derived from the scan of all pre-failure caches of the storage array. The storage array employs nonvolatile caches in conjunction with solid state drive (SSD) storage volumes, allowing post-failure recovery of recently written blocks. A cache depth at least sufficient to store the largest stripe, or set of blocks, from the host ensures recovery of the entire stripe from a collective scan of the caches of all storage volumes of the storage array.

Abstract: A standalone storage cache is responsive to a host independent of drivers or caching logic on the host. The standalone storage cache (standalone cache) interfaces between the host and corresponding storage device, and appears to each as the same I/O interface. I/O requests are sent by the host, and received/acknowledges by the standalone cache as if it were the native storage device. Similarly, the native storage device receives the I/O requests and fetches or stores the corresponding data. Caching logic in the standalone cache determines occupancy in the cache, and identifies when a request can be fulfilled by the cache rather than incurring an I/O to the storage device. No driver or other control need be resident on the host, due to independence of the standalone cache. Since the caching logic is inherent in the standalone cache, existing hosts may benefit from caching without host modification or storage volume upgrade.

Abstract: Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command.

Abstract: A disk array redundancy controller ensures integrity of a mirrored or RAID storage array supporting a host system and minimizes recovery time responsive to a storage volume failure by traversing caches of recently written blocks to identify partially flushed stripes of data and recovering the inconsistent stripes on each of the storage volumes based on a master copy derived from the scan of all pre-failure caches of the storage array. The storage array employs nonvolatile caches in conjunction with solid state drive (SSD) storage volumes, allowing post-failure recovery of recently written blocks. A cache depth at least sufficient to store the largest stripe, or set of blocks, from the host ensures recovery of the entire stripe from a collective scan of the caches of all storage volumes of the storage array.

Abstract: Executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds to a different received packet.

Abstract: Techniques and mechanisms for managing resources of an aggregate device which spans multiple physical devices of a computer platform. In an embodiment, an aggregation device coupled to a host bus of the computer platform receives resource information generated by a pre-boot software process of the computer platform. In another embodiment, the aggregation device, based on the received resource information, represents a resource in a first input/output (I/O) device to a host operating system (OS) as residing in the aggregation device, the first I/O device coupled to the aggregation device via a host bus for exchanging communications referencing a shared address space.

Abstract: Executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds to a different received packet.

Abstract: An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.

Abstract: An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.

Abstract: An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.

Abstract: Executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds to a different received packet.

Abstract: In one embodiment, the present invention includes a method for receiving an incoming packet in a packet buffer and associating it with a flow identifier. Based on the flow identifier, a core to which the incoming packet is to be directed may be determined, and a power management hint can be transmitted to cause the core to be powered up. Other embodiments are described and claimed.

Abstract: In an embodiment, a method is provided that may include providing a first address space exclusively and coherently accessible by a first processor core partition in a platform. A second address space may be provided in this embodiment that is exclusively and coherently accessible by a second processor core partition in the platform. Also in this embodiment, a third address space in the platform may be provided that is accessible, at least in part, by both the first and second processor core partitions and may be to permit communication between the first and second processor core partitions of at least one packet and at least one descriptor associated with the at least one packet. The at least one descriptor may indicate, at least in part, one or more locations in the third address space to store, at least in part, the at least one packet. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.

Abstract: In an embodiment, a method is provided that may include providing a first address space exclusively and coherently accessible by a first processor core partition in a platform. A second address space may be provided in this embodiment that is exclusively and coherently accessible by a second processor core partition in the platform. Also in this embodiment, a third address space in the platform may be provided that is accessible, at least in part, by both the first and second processor core partitions and may be to permit communication between the first and second processor core partitions of at least one packet and at least one descriptor associated with the at least one packet. The at least one descriptor may indicate, at least in part, one or more locations in the third address space to store, at least in part, the at least one packet. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.

Abstract: Methods and apparatus relating to notification of out-of-order packets are described. In an embodiment, data such as a sequence number and a flow identifier may be extracted from a packet. The extracted data may be used to check the extracted sequence number against an expected sequence number and indicate that the packet is an out-of-order packet. Other embodiments are also disclosed.

Abstract: Receive side scaling in a network system may be improved by moving the task of adapting the load distribution from the operating system (“OS”) to the network device. A load feedback mechanism may be used for the OS to report per-core load to the network device. With per-core load information from the OS as well as its own knowledge of new flows, the network device is able to map new flows to the least-utilized cores by changing these cores' entries in an indirection table in the network device directly.