Patents by Inventor Bryan G. Hickerson
Bryan G. Hickerson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11847035Abstract: Methods and systems for testing a functionality of a code modification operation are described. In an example, a processor can include a processor pipeline comprising one or more execution units. The processor pipeline can execute a first thread. The processor pipeline can further execute a second thread concurrently with the execution of the first thread. The second thread can be executed to modify the first thread using a code modification operation. The processor can further include a test module configured to validate a functionality of the code modification operation based on a result of the modified first thread.Type: GrantFiled: August 23, 2021Date of Patent: December 19, 2023Assignee: International Business Machines CorporationInventors: Charles Leverett Meissner, Elena Tsanko, Brenton Yiu, John Martin Ludden, Bryan G. Hickerson
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Publication number: 20230058716Abstract: Methods and systems for testing a functionality of a code modification operation are described. In an example, a processor can include a processor pipeline comprising one or more execution units. The processor pipeline can execute a first thread. The processor pipeline can further execute a second thread concurrently with the execution of the first thread. The second thread can be executed to modify the first thread using a code modification operation. The processor can further include a test module configured to validate a functionality of the code modification operation based on a result of the modified first thread.Type: ApplicationFiled: August 23, 2021Publication date: February 23, 2023Inventors: Charles Leverett Meissner, Elena Tsanko, Brenton Yiu, John Martin Ludden, Bryan G. Hickerson
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Patent number: 11205092Abstract: Methods, systems and computer program products for clustering simulation failures are provided. Aspects include receiving simulation data comprising a plurality of simulation failure files, generating a token for each simulation failure file of the plurality of simulation failure files, determining a token score for each token for each simulation failure file of the plurality simulation failure files, normalizing each token score for each token in the plurality of simulation failure files utilizing a weighting scheme to create a normalized token score for each token, determining a set of groups for the plurality of simulation failure files, and assigning one or more simulation failure files from the plurality of simulation failure files into a group in the set of groups based at least in part on normalized token score.Type: GrantFiled: April 11, 2019Date of Patent: December 21, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bryan G. Hickerson, John Reysa, Mohamed Baker Alawieh, Brian Kozitza, Erica Stuecheli, Tuhin Mahmud, Divya Joshi
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Publication number: 20200327364Abstract: Methods, systems and computer program products for clustering simulation failures are provided. Aspects include receiving simulation data comprising a plurality of simulation failure files, generating a token for each simulation failure file of the plurality of simulation failure files, determining a token score for each token for each simulation failure file of the plurality simulation failure files, normalizing each token score for each token in the plurality of simulation failure files utilizing a weighting scheme to create a normalized token score for each token, determining a set of groups for the plurality of simulation failure files, and assigning one or more simulation failure files from the plurality of simulation failure files into a group in the set of groups based at least in part on normalized token score.Type: ApplicationFiled: April 11, 2019Publication date: October 15, 2020Inventors: Bryan G. Hickerson, John Reysa, Mohamed Baker Alawieh, Brian Kozitza, Erica Stuecheli, Tuhin Mahmud, Divya Joshi
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Patent number: 10769334Abstract: A method, computer program product, and a fail recognition apparatus are disclosed for debugging one or more simulation fails in processor design verification that in one or more embodiments includes determining whether a prediction model exists; retrieving, in response to determining the prediction model exists, the prediction model; predicting one or more bug labels using the prediction model; determining whether a fix is available for the one or more predicted bug labels; and simulating, in response to determining the fix is available for the one or more predicted bug labels, the fix for the one or more predicted bug labels.Type: GrantFiled: November 16, 2018Date of Patent: September 8, 2020Assignee: International Business Machines CorporationInventors: Bryan G. Hickerson, Mohamed Baker Alawieh, Brian L. Kozitza, John R. Reysa, Erica Stuecheli
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Publication number: 20200159872Abstract: A method, computer program product, and a fail recognition apparatus are disclosed for debugging one or more simulation fails in processor design verification that in one or more embodiments includes determining whether a prediction model exists; retrieving, in response to determining the prediction model exists, the prediction model; predicting one or more bug labels using the prediction model; determining whether a fix is available for the one or more predicted bug labels; and simulating, in response to determining the fix is available for the one or more predicted bug labels, the fix for the one or more predicted bug labels.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: Bryan G. Hickerson, Mohamed Baker Alawieh, Brian L. Kozitza, John R. Reysa, Erica Stuecheli
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Patent number: 10528352Abstract: Blocking instruction fetching in a computer processor, includes: receiving a non-branching instruction to be executed by the computer processor; determining whether executing the non-branching instruction will cause a flush; and responsive to determining that executing the non-branching instruction will cause a flush, disabling instruction fetching for the computer processor for a time, including recoding the instruction such that the recoded instruction will be interpreted by an instruction fetch unit as an unconditional branch instruction.Type: GrantFiled: March 8, 2016Date of Patent: January 7, 2020Assignee: International Business Machines CorporationInventors: Bryan G. Hickerson, Sheldon Levenstein, David S. Levitan, Albert J. Van Norstrand, Jr.
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Publication number: 20170262286Abstract: Blocking instruction fetching in a computer processor, includes: receiving a non-branching instruction to be executed by the computer processor; determining whether executing the non-branching instruction will cause a flush; and responsive to determining that executing the non-branching instruction will cause a flush, disabling instruction fetching for the computer processor for a time, including recoding the instruction such that the recoded instruction will be interpreted by an instruction fetch unit as an unconditional branch instruction.Type: ApplicationFiled: March 8, 2016Publication date: September 14, 2017Inventors: BRYAN G. HICKERSON, SHELDON LEVENSTEIN, DAVID S. LEVITAN, ALBERT J. VAN NORSTRAND, JR.
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Patent number: 8479173Abstract: Creating one or more irritator threads on one or more processor cores in a multi-threaded multiprocessor data processing system is provided. A test generator generates non-irritator thread code for execution by a non-irritator thread and irritator thread code for execution by one or more irritator threads of the multi-threaded multiprocessor data processing system. A simulation controller instantiates the non-irritator thread to execute the non-irritator thread code and the one or more irritator threads to execute the irritator thread code. The simulation controller determines if the non-irritator thread has finished execution of the entire instruction stream of the non-irritator thread code. Responsive to the non-irritator thread finishing execution of the entire instruction stream of the non-irritator thread code, the non-irritator thread performs an operation to terminate the execution of the irritator thread code by the one or more irritator threads.Type: GrantFiled: July 9, 2008Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Bryan G. Hickerson, John M. Ludden
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Publication number: 20100011345Abstract: Creating one or more irritator threads on one or more processor cores in a multi-threaded multiprocessor data processing system is provided. A test generator generates non-irritator thread code for execution by a non-irritator thread and irritator thread code for execution by one or more irritator threads of the multi-threaded multiprocessor data processing system. A simulation controller instantiates the non-irritator thread to execute the non-irritator thread code and the one or more irritator threads to execute the irritator thread code. The simulation controller determines if the non-irritator thread has finished execution of the entire instruction stream of the non-irritator thread code. Responsive to the non-irritator thread finishing execution of the entire instruction stream of the non-irritator thread code, the non-irritator thread performs an operation to terminate the execution of the irritator thread code by the one or more irritator threads.Type: ApplicationFiled: July 9, 2008Publication date: January 14, 2010Applicant: International Business Machines CorporationInventors: Bryan G. Hickerson, John M. Ludden