Patents by Inventor Bryan Hoyer
Bryan Hoyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8156455Abstract: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.Type: GrantFiled: October 21, 2005Date of Patent: April 10, 2012Assignee: Altera CorporatonInventors: Tim Allen, Michael Fairman, Jeffrey Orion Pritchard, Bryan Hoyer
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Patent number: 8132132Abstract: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.Type: GrantFiled: March 10, 2006Date of Patent: March 6, 2012Assignee: Altera CorporationInventors: Tim Allen, Michael Fairman, Jeffrey Orion Pritchard, Bryan Hoyer
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Patent number: 8037434Abstract: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.Type: GrantFiled: August 20, 2007Date of Patent: October 11, 2011Assignee: Altera CorporationInventors: Tim Allen, Michael Fairman, Jeffrey Orion Pritchard, Bryan Hoyer
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Patent number: 7676784Abstract: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.Type: GrantFiled: October 21, 2005Date of Patent: March 9, 2010Assignee: Altera CorporationInventors: Tim Allen, Michael Fairman, Jeffrey Orion Pritchard, Bryan Hoyer
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Patent number: 7512849Abstract: A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.Type: GrantFiled: December 5, 2005Date of Patent: March 31, 2009Assignee: Altera CorporationInventors: Tim Allen, Michael Fairman, Mario Guzman, Bryan Hoyer, Chris Lane, Kerry Veenstra, Keith Duwel, Andy L. Lee
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Publication number: 20080134127Abstract: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.Type: ApplicationFiled: August 20, 2007Publication date: June 5, 2008Applicant: Altera CorporationInventors: Tim Allen, Michael Fairman, Jeffrey Orion Pritchard, Bryan Hoyer
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Publication number: 20060190907Abstract: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.Type: ApplicationFiled: March 10, 2006Publication date: August 24, 2006Applicant: Altera CorporationInventors: Tim Allen, Michael Fairman, Jeffrey Pritchard, Bryan Hoyer
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Publication number: 20060053404Abstract: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.Type: ApplicationFiled: October 21, 2005Publication date: March 9, 2006Inventors: Tim Allen, Michael Fairman, Jeffrey Pritchard, Bryan Hoyer
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Publication number: 20060036988Abstract: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.Type: ApplicationFiled: October 21, 2005Publication date: February 16, 2006Applicant: Altera CorporationInventors: Tim Allen, Michael Fairman, Jeffrey Pritchard, Bryan Hoyer
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Patent number: 7000161Abstract: A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.Type: GrantFiled: October 11, 2002Date of Patent: February 14, 2006Assignee: Altera CorporationInventors: Tim Allen, Michael Fairman, Mario Guzman, Bryan Hoyer, Chris Lane, Kerry Veenstra, Keith Duwel, Andy L. Lee
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Patent number: 6976239Abstract: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.Type: GrantFiled: June 12, 2001Date of Patent: December 13, 2005Assignee: Altera CorporationInventors: Tim Allen, Michael Fairman, Jeffrey Orion Pritchard, Bryan Hoyer
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Patent number: 4837665Abstract: A modular stage light system which features a plurality of trusses, each containing a number of stage lights. The lights are joined to a microprocessor which has an input and an output terminal adapted to be connected to a data bus. A plurality of similar trusses can be mounted on the same data bus. This modular arrangement simplifies transportation, set up and tear down of stage lights associated with theatrical and musical productions.Type: GrantFiled: December 2, 1987Date of Patent: June 6, 1989Assignee: Morpheus Lights, Inc.Inventors: Bryan Hoyer, John Richardson