Abstract: A processing module may be provided. The processing module may include a mounting member configured to structurally support a first processing unit and receive thermal energy from the first processing unit through a coupling side of the first processing unit by conduction. The processing module may also include a base member coupled to the mounting member. The base member may be configured to receive thermal energy from the mounting member. A thermal conductivity of at least one of the mounting member and the base member may be greater than about 50 Watts/meter Celsius (W/m-C). Coefficients of thermal expansion (CTEs) of the mounting member, the base member, and the coupling side of the first processing unit may be matched.

Abstract: The present disclosure is directed to automatic gain switching circuits for implementation with photodetectors that include a switchable storage network including a storage element. The switchable storage network, such as one or more capacitors, is configured and arranged to respond to a photocurrent from the photodetector and provide an increased storage for the circuit at a predetermined photocurrent. The storage elements can include one or more capacitors that can be coupled to integration capacitors of the photodetector. The switchable networks can include flux sensing switches such as MOSFETS that can activate at a desired or predetermined photocurrent level. Related methods of providing multiple gain values for a photodetector circuit, as well as focal plane arrays and imaging systems with automatic gain shifting are also described.

Abstract: A series of time delay integration TDI stages each integrate a photocurrent from a separate detector such as detectors in an array. In a first stage 20, a first integrator is initialized with a fixed bias 30, and integrates a signal from a first detector 22 during a first time interval. Next, a reset switch 26n causes that integrated first detector signal to bias a second integrator 24n. During a second integration interval, the second integrator integrates a signal from a second detector 22n. Multiple stages may be arranged in series so that an integrated signal from a previous stage biases an integrator in the current stage. At a final stage, an Nth integrator outputs the resulting signal Vfinal. Any bias used to initialize the first integrator is removed from Vfinal to achieve a total integrated signal from the detectors. A bi-directional switch 38 at each stage enables a forward or backward scan of the detectors.