Abstract: Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

Abstract: Provided are methods, systems, and computer program products to implementing a split store data queue for an out-of-order (OoO) processor. A non-limiting example of the computer-implemented method includes detecting, by the OoO processor, a mode of the OoO processor. The method further includes partitioning, by the OoO processor, a first store data queue (SDQ) and a second SDQ based at least in part on the mode of the OoO processor. The method further includes receiving, by the OoO processor, a vector operand. The method further includes storing, by the OoO processor, the vector operand in at least one of the first SDQ and the second SDQ based at least in part on the mode of the OoO processor.

Abstract: Embodiments of the present invention include methods, systems, and computer program products to implementing a split store data queue for an out-of-order (OoO) processor. A non-limiting example of the computer-implemented method includes detecting, by the OoO processor, a mode of the OoO processor. The method further includes partitioning, by the OoO processor, a first store data queue (SDQ) and a second SDQ based at least in part on the mode of the OoO processor. The method further includes receiving, by the OoO processor, a vector operand. The method further includes storing, by the OoO processor, the vector operand in at least one of the first SDQ and the second SDQ based at least in part on the mode of the OoO processor.

Abstract: Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

Abstract: Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

Abstract: Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

Abstract: The preferred embodiment of the present invention provides an improved transport demultiplexor that can receive and filter different data types before sending the data to system memory. The preferred embodiment provides a string comparator to facilitate real time filtering of continuous incoming data before loading the data into system memory. The string comparator preferably uses a bit-maskable matching filter that filters system data in real time as the data is being delivered to system memory. When data matching the filter is located, the destination address of that data is determined and delivered to the processor. This allows the processor to quickly locate the desired data and thus facilitates the real time processing of that data.

Abstract: Techniques are provided for re-mapping and interleaving transport packets of multiple transport streams for processing by a single transport demultiplexor. At least one PID re-map table is employed having re-map values indexed by n possible PID values of transport packets associated with at one transport stream of the multiple transport streams. The n possible PID values is less than or equal to the number of PID values which can be handled by the single transport demultiplexor, and is less than all possible PID values of transport packets within the multiple transport streams. The PID values within at least one transport stream are compared with the n possible PID values of the PID re-map table, and when a match is found, the table is indexed using the matching entry and a re-map value is generated therefrom. The re-map value replaces the original PID value within the transport packet.

Abstract: Positive negative and mixed digital filtering over an arbitrary variable length bit string of a datastream by evaluating bits, bytes or any other desired granularity in accordance with a mask, a filter and a not match byte. Results are accumulated over a plurality of data blocks by ANDing of compare result values similarly representing match and not match results identically depending on the not match bit except where negayive logic has been applied over an entire data block. The preferred form of the digital filter is particularly adapted to be MPEG-2 compliant.

Abstract: The preferred embodiment of the present invention provides an improved transport demultiplexor that can receive and filter different data types before sending the data to system memory. The preferred embodiment provides a string comparator to facilitate real time filtering of continuous incoming data before loading the data into system memory. The string comparator preferably uses a bit-maskable matching filter that filters system data in real time as the data is being delivered to system memory. When data matching the filter is located, the destination address of that data is determined and delivered to the processor. This allows the processor to quickly locate the desired data and thus facilitates the real time processing of that data.

Abstract: Method, system and computer products are provided for re-mapping and interleaving transport packets of multiple transport streams for processing by a single transport demultiplexor. The re-mapping and interleaving technique ensures unique identification of transport packets associated with multiple transport streams to be multiplexed onto a transport channel for demultiplexing by a single transport demultiplexor. At least one PID re-map table is employed having re-map values indexed by n possible PID values of transport packets associated with at one transport stream of the multiple transport streams. The n possible PID values is less than or equal to the number of PID values which can be handled by the single transport demultiplexor, and is less than all possible PID values of transport packets within the multiple transport streams.

Abstract: In a transport stream demultiplexor device receiving an input transport stream comprising a plurality of data packets and including a filter device for removing one or more predetermined packets to form a partial transport stream, a real-time data remultiplexing system and method comprising: a device for detecting presence of a gap in the partial transport stream where predetermined packets have been removed and generating a signal indicating the gap location; a device for directly retrieving packet data having new content from a memory storage device, and storing the retrieved packet data into a staging buffer device for queued storage prior to insertion into the partial transport stream; and, a multiplexor device responsive to the flag for pulling a queued data packet from the staging buffer device and inserting the pulled packet into the gap as the partial transport stream is being transported on a real-time basis.

Abstract: A transport demultiplexor system and queue remultiplexing methodology includes: a packet buffer for receiving data packets belonging to an input transport stream, each packet having a corresponding identifier identifying a program to which the packet belongs; a data unloader device for pulling successive packets from the packet buffer for storage in a memory storage device, and writing the pulled packets into contiguous address locations in the memory; and, a remultiplexor mechanism for generating an address offset associated with a next data packet pulled from the packet buffer to be stored in memory and writing it to a new memory location that is offset from a memory location assigned to a previously pulled packet, the offset defining a memory gap in the memory storage device capable of being filled new data content.

Abstract: The preferred embodiment of the present invention provides an improved receiver that can receive and process many different data types in addition to decoding MPEG-2 transport streams. The preferred embodiment minimizes hardware complexity by using the same loaders for both MPEG-2 and alternative stream data. The preferred embodiment utilizes a bypassable synchronizer and a bypassable packet parser to allow alternative data streams to be sent to system memory for decoding by a the host processor. When receiving MPEG-2 transport streams, the bypassable synchronizer and bypassable packet parser are used to synchronize and filter the MPEG-2 transport stream. The parsed MPEG-2 streams are then loaded into a packet buffer and passed to the video and audio decoders. When non-MPEG-2 stream data is provided, the bypassable synchronizer and bypassable packet parser instead forward the data to the packet buffer without performing synchronization or filtering.

Abstract: An on-screen display (OSD) processor, processing method and article of manufacture are provided having a color mapped mode, direct color mode, and 4:2:2 profile mode. The OSD processor implements both color mapped OSD region processing capability and direct color OSD region processing capability, along with an ability to store quantizer coefficients for the 4:2:2 profile mode of a video decoder coupled to the OSD processor. The capabilities of the OSD processor are implemented using a common embedded memory within the processor. During color mapped OSD region processing, color table data is temporarily stored within the embedded memory, while in direct color OSD region processing, direct color descriptions are stored within the embedded memory. When the video decoder is decoding a 4:2:2 formatted image, the embedded memory of the OSD processor is used to temporarily store inverse quantization data for the decode function.

Abstract: An on-screen display (OSD) processor, processing method and article of manufacture are provided having a color mapped mode, direct color mode, and 4:2:2 profile mode. The OSD processor implements both color mapped OSD region processing capability and direct color OSD region processing capability, along with an ability to store quantizer coefficients for the 4:2:2 profile mode of a video decoder coupled to the OSD processor. The capabilities of the OSD processor are implemented using a common embedded memory within the processor. During color mapped OSD region processing, color table data is temporarily stored within the embedded memory, while in direct color OSD region processing, direct color descriptions are stored within the embedded memory. When the video decoder is decoding a 4:2:2 formatted image, the embedded memory of the OSD processor is used to temporarily store inverse quantization data for the decode function.

Abstract: An on-screen display (OSD) processor, processing method and article of manufacture are provided having a color mapped mode, direct color mode, and 4:2:2 profile mode. The OSD processor implements both color mapped OSD region processing capability and direct color OSD region processing capability, along with an ability to store quantizer coefficients for the 4:2:2 profile mode of a video decoder coupled to the OSD processor. The capabilities of the OSD processor are implemented using a common embedded memory within the processor. During color mapped OSD region processing, color table data is temporarily stored within the embedded memory, while in direct color OSD region processing, direct color descriptions are stored within the embedded memory. When the video decoder is decoding a 4:2:2 formatted image, the embedded memory of the OSD processor is used to temporarily store inverse quantization data for the decode function.

Abstract: In a transport stream demultiplexor device receiving an input transport stream comprising a plurality of data packets and including a filter device for removing one or more predetermined packets to form a partial transport stream, a real-time data remultiplexing system and method comprising: a device for detecting presence of a gap in the partial transport stream where predetermined packets have been removed and generating a signal indicating the gap location; a device for directly retrieving packet data having new content from a memory storage device, and storing the retrieved packet data into a staging buffer device for queued storage prior to insertion into the partial transport stream; and, a multiplexor device responsive to the flag for pulling a queued data packet from the staging buffer device and inserting the pulled packet into the gap as the partial transport stream is being transported on a real-time basis.

Abstract: A transport demultiplexor system and queue remultiplexing methodology includes: a packet buffer for receiving data packets belonging to an input transport stream, each packet having a corresponding identifier identifying a program to which the packet belongs; a data unloader device for pulling successive packets from the packet buffer for storage in a memory storage device, and writing the pulled packets into contiguous address locations in the memory; and, a remultiplexor mechanism for generating an address offset associated with a next data packet pulled from the packet buffer to be stored in memory and writing it to a new memory location that is offset from a memory location assigned to a previously pulled packet, the offset defining a memory gap in the memory storage device capable of being filled new data content.

Abstract: Method, system and computer products are provided for re-mapping and interleaving transport packets of multiple transport streams for processing by a single transport demultiplexor. The re-mapping and interleaving technique ensures unique identification of transport packets associated with multiple transport streams to be multiplexed onto a transport channel for demultiplexing by a single transport demultiplexor. At least one PID re-map table is employed having re-map values indexed by n possible PID values of transport packets associated with at one transport stream of the multiple transport streams. The n possible PID values is less than or equal to the number of PID values which can be handled by the single transport demultiplexor, and is less than all possible PID values of transport packets within the multiple transport streams.