Patents by Inventor Bryan J. Robbins
Bryan J. Robbins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9274173Abstract: A method, system, and computer program product to test a semiconductor device are described. The system includes an input interface to receive a set of test patterns to test the semiconductor device and a user selection corresponding to a subset of the set of test patterns. The system also includes a processor to process the subset of the set of test patterns to output test data to the semiconductor device.Type: GrantFiled: September 30, 2014Date of Patent: March 1, 2016Assignee: International Business Machines CorporationInventors: Donato O. Forlenza, Orazio P. Forlenza, Michael P. Grace, Bryan J. Robbins
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Patent number: 9274172Abstract: A method, system, and computer program product to test a semiconductor device are described. The method includes receiving a set of test patterns for testing the semiconductor device and a user selecting a subset of the set of test patterns. The method also includes cataloging a content of pattern files associated with the subset of the set of test patterns to generate a catalog, and processing the catalog to output test data to the semiconductor device.Type: GrantFiled: October 17, 2013Date of Patent: March 1, 2016Assignee: International Business Machines CorporationInventors: Donato O. Forlenza, Orazio P. Forlenza, Michael P. Grace, Bryan J. Robbins
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Publication number: 20160033571Abstract: A method of performing root cause identification for a failure on an integrated circuit with a logic built-in self-test (LBIST) system and an LBIST system to perform root cause identification are described. The system includes one or more channel scan paths, each of the one or more macros associated with each of the one or more channel scan paths being executed during a test cycle, and a processor to initiate one or more of the test cycles via an LBIST controller, identify a failing test cycle among the one or more of the test cycles, identify a failing channel scan path among the one or more channel scan paths for the failing cycle, identify the one or more macros associated with the failing channel scan path, and iteratively check each of the one or more macros associated with the failing channel scan path to perform the root cause identification.Type: ApplicationFiled: September 30, 2014Publication date: February 4, 2016Inventors: Donato O. Forlenza, Orazio P. Forlenza, Bryan J. Robbins
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Publication number: 20160033570Abstract: A method of performing root cause identification for a failure on an integrated circuit with a logic built-in self-test (LBIST) system and an LBIST system to perform root cause identification are described. The method includes completing one or more cycles of test with the LBIST system, each of the one or more cycles implementing one or more macros associated with each of one or more channel scan paths. The method also includes identifying, using a processor, a failing cycle among the one or more cycles of test, identifying a failing channel scan path among the one or more channel scan paths associated with the failing cycle, and identifying the one or more macros associated with the failing channel scan path. The method further includes iteratively checking each of the one or more macros associated with the failing channel scan path to perform the root cause identification.Type: ApplicationFiled: July 30, 2014Publication date: February 4, 2016Inventors: Donato O. Forlenza, Orazio P. Forlenza, Bryan J. Robbins
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Patent number: 9244757Abstract: A method of performing root cause identification for a failure on an integrated circuit with a logic built-in self-test (LBIST) system and an LBIST system to perform root cause identification are described. The system includes one or more channel scan paths, each of the one or more macros associated with each of the one or more channel scan paths being executed during a test cycle, and a processor to initiate one or more of the test cycles via an LBIST controller, identify a failing test cycle among the one or more of the test cycles, identify a failing channel scan path among the one or more channel scan paths for the failing cycle, identify the one or more macros associated with the failing channel scan path, and iteratively check each of the one or more macros associated with the failing channel scan path to perform the root cause identification.Type: GrantFiled: September 30, 2014Date of Patent: January 26, 2016Assignee: International Business Machines CorporationInventors: Donato O. Forlenza, Orazio P. Forlenza, Bryan J. Robbins
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Patent number: 9244756Abstract: A method of performing root cause identification for a failure on an integrated circuit with a logic built-in self-test (LBIST) system and an LBIST system to perform root cause identification are described. The method includes completing one or more cycles of test with the LBIST system, each of the one or more cycles implementing one or more macros associated with each of one or more channel scan paths. The method also includes identifying, using a processor, a failing cycle among the one or more cycles of test, identifying a failing channel scan path among the one or more channel scan paths associated with the failing cycle, and identifying the one or more macros associated with the failing channel scan path. The method further includes iteratively checking each of the one or more macros associated with the failing channel scan path to perform the root cause identification.Type: GrantFiled: July 30, 2014Date of Patent: January 26, 2016Assignee: International Business Machines CorporationInventors: Donato O. Forlenza, Orazio P. Forlenza, Bryan J. Robbins
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Publication number: 20150113349Abstract: A method, system, and computer program product to test a semiconductor device are described. The method includes receiving a set of test patterns for testing the semiconductor device and a user selecting a subset of the set of test patterns. The method also includes cataloging a content of pattern files associated with the subset of the set of test patterns to generate a catalog, and processing the catalog to output test data to the semiconductor device.Type: ApplicationFiled: October 17, 2013Publication date: April 23, 2015Applicant: International Business Machines CorporationInventors: Donato O. Forlenza, Orazio P. Forlenza, Michael P. Grace, Bryan J. Robbins
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Publication number: 20150113350Abstract: A method, system, and computer program product to test a semiconductor device are described. The system includes an input interface to receive a set of test patterns to test the semiconductor device and a user selection corresponding to a subset of the set of test patterns. The system also includes a processor to process the subset of the set of test patterns to output test data to the semiconductor device.Type: ApplicationFiled: September 30, 2014Publication date: April 23, 2015Inventors: Donato O. Forlenza, Orazio P. Forlenza, Michael P. Grace, Bryan J. Robbins
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Patent number: 8443313Abstract: A method comprises generating a first behavioral model of a circuit describing a physical circuit in a first configuration. The first configuration comprises a first master latch, a first fanout path, and a logic cone. The first master latch couples to the first fanout path and is configured to receive a first data input signal. The first fanout path comprises a plurality of output sinks, each coupled to the logic cone. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit and an abstract latch clone based on the first master latch. A configuration file is generated based on the second behavioral model. The configuration file comprises information representing a plurality of instantiated latch clones based on the abstract latch clone, each configured to couple to the first data input signal and to one or more output sinks of the plurality of output sinks.Type: GrantFiled: August 18, 2010Date of Patent: May 14, 2013Assignee: International Business Machines CorporationInventors: Samuel I. Ward, Kevin F. Reick, Bryan J. Robbins, Thomas E. Rosser, Robert J. Shadowen
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Patent number: 8386230Abstract: A method includes generating a first behavioral model of a circuit, the first behavioral model describing a physical circuit in a first configuration. The first configuration comprises a first logic structure configured to generate a first intermediate signal based on a received first plurality of inputs. The first configuration further comprises a logic cone configured to generate a scan output based on the first intermediate signal and a plurality of scan inputs. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit configured to receive the scan output and the first intermediate signal. A testability model is generated based on the second behavioral model, the testability model comprising a first structural representation of the first logic structure.Type: GrantFiled: August 18, 2010Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventors: Samuel I. Ward, Kevin F. Reick, Bryan J. Robbins, Thomas E. Rosser, Robert J. Shadowen
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Publication number: 20120046921Abstract: A method includes generating a first behavioral model of a circuit, the first behavioral model describing a physical circuit in a first configuration. The first configuration comprises a first logic structure configured to generate a first intermediate signal based on a received first plurality of inputs. The first configuration further comprises a logic cone configured to generate a scan output based on the first intermediate signal and a plurality of scan inputs. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit configured to receive the scan output and the first intermediate signal. A testability model is generated based on the second behavioral model, the testability model comprising a first structural representation of the first logic structure.Type: ApplicationFiled: August 18, 2010Publication date: February 23, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Samuel I. Ward, Kevin F. Reick, Bryan J. Robbins, Thomas E. Rosser, Robert J. Shadowen
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Publication number: 20120047476Abstract: A method comprises generating a first behavioral model of a circuit describing a physical circuit in a first configuration. The first configuration comprises a first master latch, a first fanout path, and a logic cone. The first master latch couples to the first fanout path and is configured to receive a first data input signal. The first fanout path comprises a plurality of output sinks, each coupled to the logic cone. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit and an abstract latch clone based on the first master latch. A configuration file is generated based on the second behavioral model. The configuration file comprises information representing a plurality of instantiated latch clones based on the abstract latch clone, each configured to couple to the first data input signal and to one or more output sinks of the plurality of output sinks.Type: ApplicationFiled: August 18, 2010Publication date: February 23, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Samuel I. Ward, Kevin F. Reick, Bryan J. Robbins, Thomas E. Rosser, Robert J. Shadowen
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Patent number: 8095837Abstract: A test method and apparatus for randomly testing logic structures. The method includes identifying and analyzing a functional behavior of a logic structure to be covered during the random testing, modifying the logic structure such that the logic structure behaves in a functional manner during random testing, and generating patterns to exercise the modified logic structure.Type: GrantFiled: March 19, 2008Date of Patent: January 10, 2012Assignee: International Business Machines CorporationInventors: Mary P. Kusko, Barry W. Krumm, Patrick Meaney, Bryan J. Robbins
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Patent number: 7934134Abstract: A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.Type: GrantFiled: June 5, 2008Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Donato O. Forlenza, Orazio P. Forlenza, Bryan J. Robbins, Phong T. Tran
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Patent number: 7921346Abstract: A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.Type: GrantFiled: October 31, 2008Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Bryan J. Robbins, Phong T. Tran
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Publication number: 20100115337Abstract: A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.Type: ApplicationFiled: October 31, 2008Publication date: May 6, 2010Inventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Bryan J. Robbins, Phong T. Tran
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Publication number: 20090307548Abstract: A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.Type: ApplicationFiled: June 5, 2008Publication date: December 10, 2009Inventors: Donato O. Forlenza, Orazio P. Forlenza, Bryan J. Robbins, Phong T. Tran
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Publication number: 20090240995Abstract: A test method and apparatus for randomly testing logic structures. The method includes identifying and analyzing a functional behavior of a logic structure to be covered during the random testing, modifying the logic structure such that the logic structure behaves in a functional manner during random testing, and generating patterns to exercise the modified logic structure.Type: ApplicationFiled: March 19, 2008Publication date: September 24, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mary P. Kusko, Barry W. Krumm, Patrick Meaney, Bryan J. Robbins
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Patent number: 7117415Abstract: Methods and systems for reducing the volume of test data associated with built in self testing (BIST) test methodologies (e.g., logical BIST, array BIST, etc.) and pattern structures are provided. Embodiments of the present invention store a limited number of “dynamic” test parameters for each test sequence that have changed relative to a previous test sequence.Type: GrantFiled: January 15, 2004Date of Patent: October 3, 2006Assignee: International Business Machines CorporationInventors: Donato O. Forlenza, Orazio P. Forlenza, William J. Hurley, Bryan J. Robbins
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Patent number: 6990076Abstract: At least one swapper circuit is electrically connected to a bus between a plurality of entities sharing the bus. The swapper comprises a pair of series connected latches and a tristate circuits, one for each data direction, connected in parallel. The swapper acts as a revolving door, capturing data traveling from either side of the bus and shuffling the data to the other side without collision. A latch circuit is connected at either end of the bus for capturing data arriving from the other side. In addition, each of the drive entities is provided with a master/slave latched equipped with scan-in/scan-out ports, respectively, to enable testing of the circuit by allowing internal nodes of the circuit to be observed without requiring an external connection for each node accessed. In a VLSI arrangement, the scan-in/scan-out ports are connected together from a plurality of such circuits such that a variety of test patterns for various hardware configurations may be realized.Type: GrantFiled: May 18, 1999Date of Patent: January 24, 2006Inventors: Timothy G. McNamara, Bryan J. Robbins, William R. Reohr