Abstract: Configuration devices in a module. In some embodiments a radio-frequency module includes a serial bus including a first serial data line and a second serial data line. The radio-frequency module also includes a control component coupled to the serial bus and the first switch, the control component configured to determine whether first data is detected on the first serial data line, determine whether second data is detected on the second serial data line, and decode a command based on the first data and second data when the first data is detected on the first serial data line and when the second data is detected on the second serial data line.

Abstract: Configuration devices in a module. In some embodiments a radio-frequency module includes a serial bus including a first serial data line and a second serial data line. The radio-frequency module also includes a control component coupled to the serial bus and the first switch, the control component configured to determine whether first data is detected on the first serial data line, determine whether second data is detected on the second serial data line, and decode a command based on the first data and second data when the first data is detected on the first serial data line and when the second data is detected on the second serial data line.

Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.

Abstract: Configuration devices in a module. In some embodiments a radio-frequency module includes a serial bus including a first serial data line and a second serial data line. The radio-frequency module also includes a control component coupled to the serial bus and the first switch, the control component configured to determine whether first data is detected on the first serial data line, determine whether second data is detected on the second serial data line, and decode a command based on the first data and second data when the first data is detected on the first serial data line and when the second data is detected on the second serial data line.

Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.

Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.

Abstract: Configuration devices in a module. In some embodiments a radio-frequency module includes a serial bus including a first serial data line and a second serial data line. The radio-frequency module also includes a control component coupled to the serial bus and the first switch, the control component configured to determine whether first data is detected on the first serial data line, determine whether second data is detected on the second serial data line, and decode a command based on the first data and second data when the first data is detected on the first serial data line and when the second data is detected on the second serial data line.

Abstract: Configuration devices in a module. In some embodiments a radio-frequency module includes a serial bus including a first serial data line and a second serial data line. The radio-frequency module also includes a control component coupled to the serial bus and the first switch, the control component configured to determine whether first data is detected on the first serial data line, determine whether second data is detected on the second serial data line, and decode a command based on the first data and second data when the first data is detected on the first serial data line and when the second data is detected on the second serial data line.

Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.

Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.

Abstract: Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.

Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.

Abstract: Configuration devices in a module. In some embodiments a radio-frequency module includes a serial bus including a first serial data line and a second serial data line. The radio-frequency module also includes a control component coupled to the serial bus and the first switch, the control component configured to determine whether first data is detected on the first serial data line, determine whether second data is detected on the second serial data line, and decode a command based on the first data and second data when the first data is detected on the first serial data line and when the second data is detected on the second serial data line.

Abstract: Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.

Abstract: Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.

Abstract: Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.

Abstract: Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.

Abstract: A system for tuning a radio receiver includes a radio receiver configured to provide a downconverted digital error signal, a digital synthesizer circuit configured to generate a first local oscillator control signal, a digital automatic frequency control (AFC) circuit configured to generate a second local oscillator control signal, wherein the digital synthesizer circuit is enabled to generate the first local oscillator control signal when the digital AFC circuit is disabled, the first local oscillator control signal corresponds to an estimate of a desired local oscillator frequency, the digital AFC circuit is enabled to generate the second local oscillator control signal when the digital synthesizer circuit is disabled and the second local oscillator control signal corresponds to the desired local oscillator frequency.

Abstract: A system for tuning a radio receiver includes a radio receiver configured to provide a downconverted digital error signal, a digital synthesizer circuit configured to generate a first local oscillator control signal, a digital automatic frequency control (AFC) circuit configured to generate a second local oscillator control signal, wherein the digital synthesizer circuit is enabled to generate the first local oscillator control signal when the digital AFC circuit is disabled, the first local oscillator control signal corresponds to an estimate of a desired local oscillator frequency, the digital AFC circuit is enabled to generate the second local oscillator control signal when the digital synthesizer circuit is disabled and the second local oscillator control signal corresponds to the desired local oscillator frequency.

Abstract: A system for tuning a radio receiver includes a radio receiver configured to provide a downconverted digital error signal, a digital synthesizer circuit configured to generate a first local oscillator control signal, a digital automatic frequency control (AFC) circuit configured to generate a second local oscillator control signal, wherein the digital synthesizer circuit is enabled to generate the first local oscillator control signal when the digital AFC circuit is disabled, the first local oscillator control signal corresponds to an estimate of a desired local oscillator frequency, the digital AFC circuit is enabled to generate the second local oscillator control signal when the digital synthesizer circuit is disabled and the second local oscillator control signal corresponds to the desired local oscillator frequency.