Abstract: The present invention is directed to a method and system for testing systems involving high speed SERDES cores by exposing an internal nature of signals. The signals are tapped at various external test points. The present invention may take one or more test points in receive and/or transmit paths of high speed SERDES cores, and expose the test points by routing signals to the pins/balls on a chip. Programmable directing (multiplexing) of signals may be utilized to restrict number of output debug ports. Consequently, the number of the pin count required for the chip may be controlled.

Abstract: The present invention is directed to a method and system for testing systems involving high speed SERDES cores by exposing an internal nature of signals. The signals are tapped at various external test points. The present invention may take one or more test points in receive and/or transmit paths of high speed SERDES cores, and expose the test points by routing signals to the pins/balls on a chip. Programmable directing (multiplexing) of signals may be utilized to restrict number of output debug ports. Consequently, the number of the pin count required for the chip may be controlled.

Abstract: In a Framed Packet Bus (FPB) serial bus, an improved protocol and circuit layout for communication between devices grounded in the same chassis or chip. The improved protocol eliminates the requirement that bits have DC balance in their HIGH and LOW voltage levels. Consequently, bus overhead is reduced over prior techniques. In one example, data capacity utilization was increased from 80% to 95% and bus overhead was reduced from 20% to 5%. As a result of increased capacity, more packets of data may be carried across the serial bus, and any leftover bits within the frame cycle and in subsequent cycles may carry error detection information or be utilized as a control for the bus. In one preferred embodiment, the FPB serial bus configuration consists of sixteen serial lines arranged in parallel.