Abstract: High density time division busses suffer from many problems, one of which is that impedance discontinuities cause signal reflections to occur along the bus. These reflections, in turn, affect the settling time and noise margins of the bus and thus reduce the time "window" in which valid signals may be received. There is disclosed a transmission bus structure which allows for bidirectional, multi-port operation by using current drivers instead of the traditional voltage drivers for placing data signals on the bus. The transmission bus is designed in a manner which allows transmission and reception from a single clock on the same clock edge thereby substantially increasing the time allowed for transmission response and also simplifying the clock distribution requirements.

Abstract: In a memory array, dual port capability is achieved by an arrangement of the memory cells such that for each cycle of the memory operation two accesses may be performed. This result is achieved by taking advantage of the bit line precharging interval. A second bit line accessing pair is added to each memory element, and each cycle is split so that when one bit line is in the accessing mode, the other bit line is in the precharging mode. Using this technique the speed of the memory is effectively doubled.

Abstract: A time slot interchanger is disclosed for selecting and buffering digital signals between buses. The arrangement is particularly useful in forming conferences in a distributed digital time division system. In one embodiment, a clock is used to generate time signals corresponding to time slots of the first bus. These signals are sequentially provided to an associative memory and when a match occurs between the provided signal and a priorly stored time slot identity, an enable signal is provided. The enable signal has a time identity with a first bus time slot and a physical identity with a particular second bus time slot. The enable signal is used to gate into a second memory the time slot signal associated with the time identity at the storage location in the second memory corresponding with the particular time slot of the second bus associated with the enable signal. The signal samples are then sequentially removed from the second memory.

Abstract: There is disclosed an arrangement for removing error signals from a digital loop. A binary subtraction circuit is inserted in the loop and all signals passing through the circuit are reduced by a value which is dependent upon the magnitude of the accumulated signal. This arrangement serves to remove any accumulated DC offset bias from the digital signal.